JAJSFL6D April 2016 – June 2018 LMH1226
PRODUCTION DATA.
After the input signal passes through the CTLE, the equalized data is fed into the clock and data recovery (CDR) block. Using an internal PLL, the CDR locks to the incoming equalized data and recovers a clean internal clock to re-sample the equalized data. The LMH1226 CDR is able to tolerate high input jitter, tracking low frequency input jitter below the PLL bandwidth while reducing high frequency input jitter above the PLL bandwidth.
The supported data rates are listed in Table 3. IN1 locks to either SMPTE or 10 GbE data rates according to the IN_OUT_SEL pin logic shown previously in Table 2. When locked to SMPTE data rates according to IN_OUT_SEL pin logic, IN1 can be programmed to lock to the 10 GbE data rate, and vice versa, via register control by applying the appropriate override bit values. For more information, refer to the LMH1226 Register Map.
| IN_OUT_SEL
LEVEL |
DATA RATE | RECLOCKER MODE |
|---|---|---|
| H, F | 11.88 Gbps, 5.94 Gbps, 2.97 Gbps, 1.485 Gbps, 270 Mbps(1) | Reclocker Enabled |
| 125 Mbps | Reclocker Disabled (CDR Bypassed) | |
| R, L | 10.3125 Gbps | Reclocker Enabled |
| 1.25 Gbps | Reclocker Disabled (CDR Bypassed) |
NOTE
If the selected data rate (SMPTE or 10 GbE) is changed while the device is operating with active data, a CDR reset and release is required for the CDR to re-acquire lock. If the input data signal is toggled off and on after the selected data rate is changed, the Carrier Detect circuit will reset the CDR. In this case, no register write is needed for the CDR to re-acquire lock.