Table 2 lists the known supported standard timing formats and includes the relevant parameters that can be used to configure the LMH1982 for the input reference and output timing. For the related programming instructions, see sections Input Reference and Output Clocks and TOF.

7.4.1.1 Free Run Mode

The LMH1982 will enter Free Run mode when GNLK is set to 0. In Free Run mode, the VCXO will be free-running and independent of the input reference, and the output clocks will maintain phase lock to the VCXO clock reference. Therefore, the output clocks will have the same accuracy as the VCXO clock reference.

The LMH1982 provides the designer with the option to define the VCXO's free run control voltage by external biasing of the VC_FREERUN input (pin 1). The analog bias voltage applied to the VC_FREERUN input will be connected to the LPF output (pin 31) though an internal switch (non-buffered, low impedance), as shown in the Functional Block Diagram. The resultant voltage at the LPF output will drive the control input of the VCXO to set its free run output frequency. Thus, the pull range of the VCXO imparts the same pull range on the free run output clocks.

If VC_FREERUN is left floating, the VCXO control voltage will be pulled to GND potential as the residual charge stored across the loop filter will discharge through any existing leakage path.

7.4.1.2 Genlock Mode

The LMH1982 will enter Genlock mode when GNLK is set to 1. In Genlock mode, PLL 1 can be phase locked to the reference H sync input of the selected port; once the VCXO clock reference is locked and stable, the output clocks and TOF pulse can be aligned and phase locked to the reference. The LMH1982 supports cross-locking, which allows the outputs to be frame-locked to a reference format that is different from the output format.

To genlock the outputs, the following programming sequence is suggested:

1. Program the output clock frequency for the desired output format. See Programming the Output Clock Frequencies for more information.
2. Program the output TOF timing for the desired output format. See Programming the Output Format Timing for more information. It is required to complete this step for proper output clock initialization (alignment) even if the TOF pulse is not required.
3. Program the PLL 1 divider registers for the input reference format. See Programming the PLL 1 Dividers for more information.
4. Program GNLK = 1 to enable Genlock mode.

NOTE

When Genlock mode is enabled, the LMH1982 will attempt to phase lock the PLLs to the input reference regardless of input timing stability. Timing errors or instability on the inputs will cause the PLLs and outputs to also have instability. If output stability is a consideration during periods of input uncertainty, it is suggested to gate off the input signals from the LMH1982 until they are completely stable. Input signal gating can be achieved externally using a discrete or FPGA logic buffer with Hi-Z (tri-state) output and a pull-up or pull-down resistor, depending on the input pulse signal polarity.

5. Program the output initialization to the desired reference frame. See Programming the Output Initialization Sequence for more information.

7.4.1.2.1 Genlock Mode State Diagram

Figure 7 shows the Genlock mode state diagram for different input reference and PLL lock conditions. It also includes Free Run and Holdover states for the loss of reference operation, specified by the HOLDOVER bit (register 00h). Each state indicates the NO_REF and NO_LOCK status flag output conditions.

Figure 7. Genlock Mode State Diagram

7.4.1.2.1.1 Loss of Reference (LOR)

By configuring the HOLDOVER bit, the LMH1982 can default to either Free Run or Holdover operation when a loss of reference (LOR) occurs in Genlock mode.

If HOLDOVER = 0 when a LOR occurs, the LMH1982 will default to Free run operation (Free Run during LOR) until a reference is reapplied.

If HOLDOVER = 1 when a LOR occurs, the LMH1982 will default to Holdover operation (Holdover during LOR) until a reference is reapplied.

When the input reference is reapplied, the LMH1982 will immediately attempt to phase lock the output clocks to the reference.

7.4.1.2.1.1.1 Free Run during LOR

Free Run mode (GNLK = 0) differs from Free Run operation due to LOR in Genlock mode (GNLK = 1) in the following way:

• In Free Run mode, the outputs will free run regardless of the presence or loss of reference.
• In Genlock mode, the outputs will free run only during LOR; once a reference is present, free run operation will cease as the PLLs will immediately attempt to phase lock the output clocks to the reference.

7.4.1.2.1.1.2 Holdover during LOR

In Holdover operation, the LPF output is put into high impedance mode, which allows the loop filter to temporarily hold the residual charge stored across it (i.e. the control voltage) immediately after LOR is indicated by the NO_REF status flag. Holdover operation can help to temporarily sustain the output clock accuracy upon LOR. The duration that the residual control voltage level can be sustained within a tolerable level depends primarily on the charge leakage on the loop filter. A typical VCXO has an input impedance of several tens of kΩ, which will be the dominant leakage path seen by the loop filter. As the leakage current discharges the residual control voltage to GND, the output frequencies of the VCXO and LMH1982 will drift accordingly. If a longer time constant is required, a precision op amp with low input bias current and rail-to-rail input and output (e.g. LMP7701) can be used to buffer the control voltage. The buffer will isolate the relatively low input impedance of the VCXO and reduce the charge leakage on the loop filter during Holdover.

The output frequency accuracy will degrade as the VCXO accuracy drifts with the decaying control voltage. Moreover, because the H_ERROR setting (register 00h) affects the reference error threshold for LOR indication, a higher setting for H_ERROR may result in reduced output accuracy upon LOR indication compared to when H_ERROR = 0. For more information on programming H_ERROR, see Programming the Loss of Reference (LOR) Threshold.

Figure 8. Loop Filter with Optional Op Amp to Isolate VCXO's Low Input Impedance

7.5.1.1 Write Sequence

The write sequence begins with a start condition, which consists of the master pulling SDA low while SCL is held high. The slave device address is sent next. The address byte is made up of an address of seven bits (7:1) and the read/write bit (0). Bit 0 is low to indicate a write operation. Each byte that is sent is followed by an acknowledge (ACK) bit. When SCL is high the master will release the SDA line. The slave must pull SDA low to acknowledge. The address of the register to be written to is sent next. Following the register address and the ACK bit, the data byte for the register is sent. When more than one data byte is sent, it is automatically incremented into the next address location. See Figure 9. Note that each data byte is followed by an ACK bit.

Figure 9. LMH1982 Write Sequence

7.5.1.2 Read Sequence

Read sequences are comprised of two I²C transfers. The first is the address access transfer, which consists of a write sequence that transfers only the address to be accessed. The second is the data read transfer, which starts at the address accessed in the first transfer and increments to the next address per data byte read until a stop condition is encountered.

The address access transfer shown in Figure 10 consists of a start pulse, the slave device address including the read/write bit (a zero, indicating a write), then its ACK bit. The next byte is the address to be accessed, followed by the ACK bit and the stop bit to indicate the end of the address access transfer.

The subsequent read data transfer shown in Figure 11 consists of a start pulse, the slave device address including the read/write bit (a one, indicating a read) and the ACK bit. The next byte is the data read from the initial access address. Subsequent read data bytes will correspond to the next increment address locations. Each data byte is separated from the other data bytes by an ACK bit.

Figure 10. LMH1982 Read Sequence – Address Access Transfer

Figure 11. LMH1982 Read Sequence – Data Read Transfer

7.5.1.3 I²C Enable Control Pin

When the active low input I2C_ENABLE = 0, the LMH1982 will enable I²C communication via its fixed slave address; otherwise, the LMH1982 will not respond. For applications with multiple LMH1982 devices on the same I²C bus, the I²C enable function can be useful for writing data to a specific device(s) and for reading data from an individual device to prevent bus contention. For single chip applications, the I2C_ENABLE input can be tied to GND to keep the I²C interface enabled.

Table 3. I²C Interface Control Register Map⁽¹⁾

7.6.1.1 Genlock and Input Reference Control Registers

Register 00h

Bits 2-0: H Input Error Max Count (H_ERROR)

The H_ERROR bits control the reference detector's error threshold, which determines the maximum number of missing H sync pulses before indicating a LOR. See Programming the Loss of Reference (LOR) Threshold for more information.

Bit 3: Holdover on Loss of Reference (HOLDOVER)

The HOLDOVER bit controls the operating mode when a loss of reference occurs. See Loss of Reference (LOR) for more information.

Bit 4: Reference Select (RSEL)

The RSEL bit selects either REF_A or REF_B inputs as the reference to genlock the outputs when I²C_RSEL = 1.

 RSEL = 0: Select REF_A inputs.

 RSEL = 1: Select REF_B inputs.

If PIN6_OVRD = 1 (register 02h), then reference selection must be controlled by programming RSEL, regardless of I²C_RSEL. When PIN6_OVRD = 0 and I²C_RSEL = 0, then reference selection is controlled using the REF_SEL input pin and the RSEL bit is ignored.

Bit 5: Reference Select Control via I²C (I²C_RSEL)

By programming I²C_RSEL, reference selection can be controlled either via I²C or the REF_SEL input pin.

 I²C_RSEL = 1: Control reference selection by programming RSEL.

 I²C_RSEL = 0: Control reference selection via the REF_SEL input pin.

Bit 6: Mode Select (GNLK)

The GNLK bit selects the operating mode when I²C_GNLK = 1. See Modes of Operation for more information.

 GNLK = 0: Selects Free Run mode.

 GNLK = 1: Selects Genlock mode.

If I²C_GNLK = 0, then the operating mode will be controlled using the GENLOCK input pin and the GNLK bit will be ignored.

Bit 7: Mode Select via I²C (I²C_GNLK)

By programming I²C_GNLK, mode selection can be controlled either via I²C or the GENLOCK input pin.

 I²C_GNLK = 1: Control mode selection by programming GNLK.

 I²C_GNLK = 0: Control mode selection through the GENLOCK input pin.

7.6.1.2 Genlock Status And Lock Control Register

Register 01h

Bit 0: Reference Status (REF_VALID)

REF_VALID is a read-only bit and indicates the presence or loss of reference on the selected reference port in Genlock mode. The NO_REF output flag is an inverted copy of REF_VALID. See Reference Detection for more information.

 REF_VALID = 0: Indicates loss of reference (LOR).

 REF_VALID = 1: Indicates valid reference.

In Free Run mode, REF_VALID will be set to 0 to indicate the absence of any input pulses at the selected HREF port.

Bit 1: SD Clock PLL Lock Status (SD_LOCK)

SD_LOCK is a read-only bit and indicates PLL lock status of the selected SD clock. See PLL Lock Detection for more information.

 SD_LOCK = 0: Indicates loss of lock.

 SD_LOCK = 1: Indicates valid lock.

Bit 2: HD Clock PLL Lock Status (HD_LOCK)

HD_LOCK is a read-only bit and indicates PLL lock status of the selected HD clock. See PLL Lock Detection for more information.

 HD_LOCK = 0: Indicates loss of lock.

 HD_LOCK = 1: Indicates valid lock.

Bits 7-3: Lock Control (LOCK_CTRL)

LOCK_CTRL controls the phase error threshold of PLL 1's lock detector. A larger value for LOCK_CTRL will yield shorter lock indication time (although not actual lock time) at the expense of higher output phase error when lock is initially indicated, whereas a smaller value will yield the opposite effect. See Programming the PLL Lock Threshold for more information.

7.6.1.3 Input Control Register

Register 02h

Bit 0: VREF_B Input Signal Polarity (POL_VB)

This bit should be programmed to match the input signal polarity at the VREF_B input pin.

 POL_VB = 0: Negative polarity or active low signal.

 POL_VB = 1: Positive polarity or active high signal.

Bit 1: HREF_B Input Signal Polarity (POL_HB)

This bit should be programmed to match the input signal polarity at the HREF_B input pin. The positive edge of the output clock will be phase locked to the active edge of the H sync input signal.

 POL_HB = 0: Negative polarity or active low signal.

 POL_HB = 1: Positive polarity or active high signal.

Bit 2: VREF_A Input Signal Polarity (POL_VA)

This bit should be programmed to match the input signal polarity at the VREF_A input pin.

 POL_VA = 0: Negative polarity or active low signal.

 POL_VA = 1: Positive polarity or active high signal.

Bit 3: HREF_A Input Signal Polarity (POL_HA)

This bit should be programmed to match with the input signal polarity at HREF_A input pin. The positive edge of the output clock will be phase locked to the active edge of the H sync input signal.

 POL_HA = 0: Negative polarity or active low signal.

 POL_HA = 1: Positive polarity or active high signal.

Bit 4: 27 MHz Reference Control (27M_REF)

Instead of an H sync signal, a 27 MHz clock signal can be applied to the selected HREF input to phase lock the output clocks. If a 27 MHz clock is used as a reference, then a value of 1 should be programmed to 27M_REF, REF_DIV_SEL, and FB_DIV.

 27M_REF = 0: H sync input signal.

 27M_REF = 1: 27 MHz clock input signal. Also, set REF_DIV_SEL =1 and FB_DIV = 1

Bit 5: Pin 6 Override (PIN6_OVRD)

The PIN6_OVRD bit can be programmed to override the default reference selection capability on pin 6 and instead use pin 6 as an logic pulse input to initialize or reset the internal counters for output initialization.

PIN6_OVRD = 0: Allows a logic level input to be applied to pin 6 for reference selection if RSEL_I²C = 0 (register 00h). If RSEL_I²C = 1, then pin 6 is ignored and reference selection is controlled via I²C; additionally, outputs must be initialized via I²C by programming TOF_INIT and EN_TOF_RST (register 0Ah).

PIN6_OVRD = 1: Allows an TOF Init pulse to be applied to pin 6 for output initialization if EN_TOF_RST = 1. If EN_TOF_RST = 0, then any TOF Init pulse received at pin 6 will be ignored. Additionally, reference selection must be controlled via I²C, regardless of I²C_RSEL.

Bits 7-6: Reserved (RSV)

These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as specified in Table 3.

7.6.1.4 PLL 1 Divider Register

Register 03h

Bits 1-0: Reference Divider Selection (REF_DIV_SEL)

REF_DIV_SEL selects the reference divider value according to the selection table in Table 1. See Programming the PLL 1 Dividers for more information.

The reference divider value is the denominator of PLL 1's divider ratio:

Feedback divider value / Reference divider value = 27 MHz / Hsync input frequency

The numerator and denominator values of the divider ratio should be reduced to their lowest factors to be compatible with the range of divider values offered by REF_DIV_SEL and FB_DIV. These registers must be programmed correctly to phase lock the 27 MHz VCXO PLL and output clocks to the input reference. See Table 2 for the suggested divider settings for the supported timing formats.

Bits 7-3: Reserved (RSV)

These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as specified in Table 3.

Register 04h

Bits 7-0: Feedback Divider (FB_DIV)

This register contains the 8 LSBs of FB_DIV. The feedback divider value is the numerator of PLL 1's divider ratio. FB_DIV should be programmed using the feedback divider value after the divide ratio has been reduced to its lowest factors. Refer to the description for register 03h, and see Table 2 for the suggested divider settings for the supported timing format.

Register 05h

Bits 4-0: Feedback Divider (FB_DIV)

This register contains the 5 MSBs of FB_DIV. See the description for register 04h.

Bits 7-5: These non-programmable bits contain zeros.

7.6.1.5 PLL 4 Charge Pump Current Control Register

Register 06h

Bits 3-0: Charge Pump Current Control for PLL 4 (ICP4)

ICP4 can be programmed to specify charge pump current for PLL 4, which generates the 67.5 MHz SD clock.

The PLL 4 charge pump current increases linearly with the effective value. Reducing the effective value of the charge pump current will lower its loop bandwidth at the expense of reduced PLL stability. An effective value of 0 (ICP4 = 1000b) should not be programmed since this corresponds to 0 µA nominal current and will cause PLL 4 to lose phase lock.

Bits 7-4: Reserved (RSV)

These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as specified in Table 3.

Register 07h

Bits 7-0: Reserved (RSV)

This register is reserved. If necessary, only write the default data (00h) to register 07h as specified in Table 3.

7.6.1.6 Output Clock and TOF Control Register

Register 08h

Bit 0: SD Clock Output Frequency Select (SD_FREQ)

This bit sets the clock frequency of the SD_CLK output pair.

 SD_FREQ = 0: Selects 27 MHz from PLL 1.

 SD_FREQ = 1: Selects 67.5 MHz from PLL 4.

Bit 1: SD Clock Output Mode (SD_HIZ)

Set the SD_HIZ bit to 1 to put the SD_CLK output pair in high-impedance (Hi-Z) mode; otherwise, the SD_CLK output will be enabled.

Bit 3-2: HD Clock Output Frequency Select (HD_FREQ)

These bits set the clock frequency of the HD_CLK output pair.

 HD_FREQ = 0h: Selects 74.25 MHz from PLL 2.

 HD_FREQ = 1h: Selects 74.176 MHz from PLL 3.

 HD_FREQ = 2h: Selects 148.5 MHz from PLL 2.

 HD_FREQ = 3h: Selects 148.35 MHz from PLL 3.

Bit 4: HD Clock Output Mode (HD_HIZ)

Set the HD_HIZ bit to 1 to put the HD_CLK output pair in high-impedance (Hi-Z) mode; otherwise, the HD_CLK output will be enabled.

Bit 5: Top of Frame Output Mode (TOF_HIZ)

Set the TOF_HIZ bit to 1 to put the TOF output pin in high-impedance (Hi-Z) mode; otherwise, the output will be enabled.

Bits 7-6: Reserved (RSV)

These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as specified in Table 3.

7.6.1.7 TOF Configuration Registers

Register 09h

Bits 7-0: TOF Reset (TOF_RST)

This register contains the 8 LSBs of TOF_RST. When PLL 1 is phase locked to the reference, both H sync and V sync inputs are used to reset the frame-based counters used for output TOF generation. The numerator value of the reduced frame rate ratio should be programmed to TOF_RST. See Input-Output Frame Rate Ratio for more information.

Once TOF_RST is programmed, the outputs must be properly initialized by either programming TOF_INIT or otherwise using an external TOF Init pulse (when PIN6_OVRD = 1).

Register 0Ah

Bits 4-0: TOF Reset (TOF_RST)

This register contains the 5 MSBs of TOF_RST. See the description for register 09h.

Bit 5: Output Initialization (TOF_INIT)

After enabling output alignment mode (EN_TOF_RST = 1), the TOF_INIT bit should be programmed to reset the internal counters and initialize (align) the outputs to the desired reference frame. The output initialization is triggered by programming a positive bit transition (0 to 1) to TOF_INIT. See Programming the Output Initialization Sequence for more information.

Bit 6: TOF Pulse Output Polarity (POL_TOF)

This bit should be programmed to the desired TOF pulse polarity at the TOF output.

 POL_TOF = 0: Negative polarity or active low signal.

 POL_TOF = 1: Positive polarity or active high signal.

Bit 7: Output Alignment Mode (EN_TOF_RST)

This bit must be set (EN_TOF_RST = 1) to enable output alignment mode prior to initialization per Programming the Output Initialization Sequence. It is recommended to clear this bit (EN_TOF_RST = 0) immediately after the output initialization sequence has been programmed to prevent excessive output jitter, as described in Output Disturbance While Output Alignment Mode Enabled.

Register 0Bh

Bits 7-0: Total Pixels per Line for the Output Format (TOF_PPL)

This register contains the 8 LSBs of TOF_PPL. TOF_PPL should be programmed with total pixels per line for the desired output format. TOF_PPL is used in specifying the output frame rate. This should be specified prior to programming the output initialization sequence. See Output Frame Timing for more information.

Register 0Ch

Bits 4-0: MSBs of Total Pixels per Line for the Output Format (TOF_PPL)

This register contains the 5 MSBs of TOF_PPL. See the description for register 0Bh.

Bit 5: Output Clock Select for Output Top of Frame (TOF_CLK)

This bit should be programmed to select the output TOF clock reference according to the desired output format. The selected TOF clock frequency is used in specifying the output frame rate. Any output format, including HD, can use 27 MHz as the TOF clock to generate its TOF pulse by programming the output counter values corresponding to the 27 MHz SD clock as shown in Table 2. See sections Output TOF Clock and Output Frame Timing.

 TOF_CLK = 0: Selects the SD_CLK output as the output clock reference, where the SD frequency is set by SD_FREQ.

 TOF_CLK = 1: Selects the HD_CLK output as the output clock reference.

Bit 7-6: These non-programmable bits contain zeros.

Register 0Dh

Bits 7-0: LSBs of Total Lines per Frame for the Output Format (TOF_LPFM)

This register contains the 8 LSBs of TOF_LPFM. TOF_LPFM should be programmed with the total lines per frame for the desired output format. TOF_LPFM is used in specifying the output frame rate. This should be specified prior to programming the output initialization sequence. See Output Frame Timing for more information.

Register 0Eh

Bits 3-0: MSBs of Total Lines per Frame for the Output Format (TOF_LPFM)

This register contains the 4 MSBs of TOF_LPFM. See the description for register 0Dh.

Bit 7-5: These non-programmable bits contain zeros.

Register 0Fh

Bits 7-0: LSBs of Total Lines per Frame for the Input Reference Format (REF_LPFM)

This register contains the 8 LSBs of REF_LPFM. REF_LPFM should be programmed with the total lines per frame for the input reference format. REF_LPFM is used in specifying the reference frame rate. This should be specified prior to programming the output initialization sequence (Reference Frame Timing).

Register 10h

Bits 3-0: MSBs of Total Lines per Frame for the Input Reference Format (REF_LPFM)

This register contains the 4 MSBs of REF_LPFM. See the description for register 0Fh.

Bit 7-4: These non-programmable bits contain zeros.

Register 11h

Bits 7-0: LSBs of Output Frame Offset (TOF_OFFSET)

This register contains the 8 LSBs of TOF_OFFSET. TOF_OFFSET should be programmed with the desired line offset to delay or advance the output timing relative to the reference frame. This should be specified prior to programming the output initialization sequence. See Output Frame Line Offset for more information.

Register 12h

Bits 3-0: MSBs of Line Offset for the Output Top of Frame (TOF_OFFSET)

This register contains the 4 MSBs of TOF_OFFSET. See the description for register 11h.

Bit 7-4: These bits contain zeros (non-programmable)

7.6.1.8 PLL 1, 2, 3 Charge Pump Current Control Registers

Register 13h

Bits 4-0: PLL 1 Charge Pump Current Control (ICP1)

ICP1 can be programmed to specify the charge pump current for PLL 1, which generates 27 MHz from the VCXO output. The PLL 1 charge pump current, or I_CP1, is one of the loop gain parameters can be programmed to set and optimize PLL 1's loop response. For more information on setting the loop response, see Loop Response.

To minimize lock time, using a large or maximum I_CP1 can result in faster PLL settling time due to a wider loop bandwidth. Once phase lock has been achieved, using a lower I_CP1 (that yields sufficient stability) can provide good input jitter rejection due to a narrower loop bandwidth; this can be helpful to minimize low-frequency input jitter from being transferred to the output clocks.

 ICP1 register range = 0 to 31d; 0 to 2d are not recommended

 I_CP1 current = ICP1 x 31.25 µA (nominal current step)

Examples:

 ICP1 = 8d (default) gives I_CP1 = 250 µA nominal

 ICP1 = 31d (max) gives I_CP1 = 968.75 µA nominal

Bits 7-5: Reserved (RSV)

These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as specified in Table 3.

Register 14h

Bits 3-0: PLL 3 Charge Pump Current Control (ICP3)

ICP3 can be programmed to specify the charge pump current for PLL 3, which generates the 74.176 and 148.35 MHz HD clock outputs. Reducing the value of ICP3 will reduce the PLL 3 charge pump current and lower its loop bandwidth at the expense of reduced PLL stability. An ICP3 value of 0 should not be programmed since this corresponds to 0 µA nominal current, which will cause PLL 3 to lose phase lock or otherwise be unstable.

 ICP3 register range = 0 to 15d

Bit 7-4: PLL 2 Charge Pump Current Control (ICP2)

ICP2 can be programmed to specify the charge pump current for PLL 2, which generates the 74.25 and 148.5 MHz HD clock outputs. Reducing the value of ICP2 will reduce the PLL 2 charge pump current and lower its loop bandwidth at the expense of reduced PLL stability. An ICP2 value of 0 should not be programmed since this corresponds to 0 µA nominal current, which will cause PLL 2 to lose phase lock or otherwise be unstable.

 ICP2 register range = 0 to 15d

7.6.1.9 Reserved Registers

Register 15h-1Fh

This register is reserved. Do not program any data to these registers.