SNLS289D April   2008  – September 2015 LMH1982

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supported Standards and Timing Formats
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 Free Run Mode
        2. 7.4.1.2 Genlock Mode
          1. 7.4.1.2.1 Genlock Mode State Diagram
            1. 7.4.1.2.1.1 Loss of Reference (LOR)
              1. 7.4.1.2.1.1.1 Free Run during LOR
              2. 7.4.1.2.1.1.2 Holdover during LOR
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Protocol
        1. 7.5.1.1 Write Sequence
        2. 7.5.1.2 Read Sequence
        3. 7.5.1.3 I2C Enable Control Pin
    6. 7.6 Register Maps
      1. 7.6.1 I2C Interface Control Register Definitions
        1. 7.6.1.1 Genlock and Input Reference Control Registers
        2. 7.6.1.2 Genlock Status And Lock Control Register
        3. 7.6.1.3 Input Control Register
        4. 7.6.1.4 PLL 1 Divider Register
        5. 7.6.1.5 PLL 4 Charge Pump Current Control Register
        6. 7.6.1.6 Output Clock and TOF Control Register
        7. 7.6.1.7 TOF Configuration Registers
        8. 7.6.1.8 PLL 1, 2, 3 Charge Pump Current Control Registers
        9. 7.6.1.9 Reserved Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 148.35 MHz PLL Initialization Sequence
      2. 8.1.2 Enabling Genlock Mode
      3. 8.1.3 Output Disturbance While Output Alignment Mode Enabled
      4. 8.1.4 Evaluating the LMH1982
      5. 8.1.5 Input Reference
        1. 8.1.5.1 Reference Frame Decoder
      6. 8.1.6 Output Clocks and TOF
        1. 8.1.6.1 Programming the Output Clock Frequencies
        2. 8.1.6.2 Programming the Output Format Timing
          1. 8.1.6.2.1 Output TOF Clock
          2. 8.1.6.2.2 Output Frame Timing
            1. 8.1.6.2.2.1 HD Format TOF Generation Using a 27-MHz TOF Clock
          3. 8.1.6.2.3 Reference Frame Timing
          4. 8.1.6.2.4 Input-Output Frame Rate Ratio
          5. 8.1.6.2.5 Output Frame Line Offset
        3. 8.1.6.3 Programming the Output Initialization Sequence
          1. 8.1.6.3.1 TOF Output Delay Considerations
          2. 8.1.6.3.2 Output Clock Initialization Without TOF
        4. 8.1.6.4 Output Behavior Upon Loss Of Reference
      7. 8.1.7 Reference And Pll Lock Status
        1. 8.1.7.1 Reference Detection
          1. 8.1.7.1.1 Programming the Loss of Reference (LOR) Threshold
        2. 8.1.7.2 PLL Lock Detection
          1. 8.1.7.2.1 Programming the PLL Lock Threshold
          2. 8.1.7.2.2 PLL Lock Status Instability
      8. 8.1.8 Loop Response
        1. 8.1.8.1 Loop Response Design Equations
          1. 8.1.8.1.1 Loop Response Optimization Tips
          2. 8.1.8.1.2 Loop Filter Capacitors
        2. 8.1.8.2 Lock Time Considerations
        3. 8.1.8.3 VCXO Considerations
        4. 8.1.8.4 Free Run Output Jitter
    2. 8.2 Typical Applications
      1. 8.2.1 Analog Reference Genlock for Triple-Rate SDI Video
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Programming the PLL 1 Dividers
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Procedure for Designing the PLL 1 Dividers
      2. 8.2.2 SDI Reference Genlock for Triple-Rate SDI Video
      3. 8.2.3 Triple-Rate SDI Loop-through
      4. 8.2.4 Combined Genlock or Loop-Through for Triple-Rate SDI Video
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RTV Package
32-Pin WQFN
Top View
LMH1982 30052402.gif

Pin Functions

PIN I/O SIGNAL LEVEL DESCRIPTION
NO. NAME
– DAP — Supply Die Attach Pad (Connect to GND)
1 VC_FREERUN I Analog Free Run Control Voltage Input
2, 10, 18, 22, 26, 30 GND — Supply Ground
3, 21, 27, 28, 32 VDD — Supply 3.3-V Supply(1)
4 HREF_A I LVCMOS H sync Input, Reference A
5 VREF_A I LVCMOS V sync Input, Reference A
6 REF_SEL I LVCMOS Reference Select(2)(3)
7 HREF_B I LVCMOS H sync Input, Reference B
8 VREF_B I LVCMOS V sync Input, Reference B
9 DVDD — Supply 2.5-V Supply(4)
11 SDA I/O I2C I2C Data(5)
12 SCL I I2C I2C Clock(5)
13 I2C_ENABLE I LVCMOS I2C Enable
14 GENLOCK I LVCMOS Mode Select(6)
15 RESET I LVCMOS Device Reset
16 NO_REF O LVCMOS Reference Status Flag
17 NO_LOCK O LVCMOS Lock Status Flag
19, 20 HD_CLK, HD_CLK O LVDS HD Clock Output
23, 24 SD_CLK, SD_CLK O LVDS SD Clock Output
25 TOF O LVCMOS Top of Frame Pulse
29 VCXO I LVCMOS VCXO Clock Input
31 LPF O Analog VCXO PLL Loop Filter
(2) To control reference selection via the REF_SEL pin instead of the I2C interface (default), program I2C_RSEL = 0 (register 00h).
(3) To override reference control through pin 6 and instead use pin 6 as an logic input for output initialization, program PIN6_OVRD = 1 (register 02h); accordingly, the TOF_INIT bit (register 0Ah) will be ignored and reference selection must be controlled through I2C.
(4) Must be ≤ VDD + 0.3 V. Refer to Power Supply Sequencing.
(5) SDA and SCL pins each require a 4.7-kΩ (typical) pullup resistor to the VDD supply.
(6) To control mode selection through the GENLOCK pin instead of the I2C interface (default), program I2C_GNLK = 0 (register 00h).