SNLS289D April 2008 – September 2015 LMH1982
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage, VDD | 3.6 | V | ||
Supply Voltage, DVDD | 2.75 | V | ||
Input Voltage (any input) | −0.3 | VDD +0.3 | V | |
Lead Temperature (Soldering 10 sec.) | 300 | °C | ||
Junction Temperature, TJMAX | 150 | °C | ||
Storage Temperature | −65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Machine Model | ±200 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | 3.135 | 3.465 | V | |
DVDD | 2.375 | 2.625 | V | |
Input Voltage | 0 | VDD | V | |
Temperature, TA | 0 | 70 | °C |
THERMAL METRIC(1) | LMH1982 | UNIT | |
---|---|---|---|
RTV (WQFN) | |||
32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 33 | °C/W |
PARAMETER | TEST CONDITIONS | MIN(2) | TYP(1) | MAX(2) | UNIT | ||
---|---|---|---|---|---|---|---|
IVDD | VDD Supply Current | Default register settings, no input reference, 27-MHz VCXO and loop filter connected, 100-Ω differential load on SD_CLK and HD_CLK outputs; no load on all other outputs | 47 | mA | |||
IDVDD | DVDD Supply Current | 39 | mA | ||||
IVDD | VDD Supply Current | VDD = 3.465 V, DVDD = 2.625 V, Genlock mode, 1080p/59 output timing, HD_CLK = 148.35 MHz, SD_CLK = 67.5 MHz, 100-Ω differential load on SD_CLK and HD_CLK outputs; no load on all other outputs | 57 | mA | |||
At the temperature extremes | 70 | ||||||
IDVDD | DVDD Supply Current | 44 | mA | ||||
At the temperature extremes | 60 | ||||||
FREE RUN VOLTAGE CONTROL INPUT (PIN 1) | |||||||
VIL | Low Analog Input Voltage | See (3) | 0 | V | |||
VIH | High Analog Input Voltage | See (3) | VDD | V | |||
REFERENCE INPUTS (PINS 4, 5, 7, 8) | |||||||
VIL | Low Input Voltage | IIN = ±10 μA | 0 | 0.3 VDD | V | ||
VIH | High Input Voltage | IIN = ±10 µA | 0.7 VDD | VDD | V | ||
ΔTHV | H-V Sync Timing Offset | Input timing offset measured from H sync to V sync pulse leading edges (4) | 2.0 | μs | |||
DIGITAL CONTROL INPUTS (PINS 6, 13, 14, 15) | |||||||
VIL | Low Input Voltage | IIN = ±10 µA | 0 | 0.3 VDD | V | ||
VIH | High Input Voltage | IIN = ±10 µA | 0.7 VDD | VDD | V | ||
I2C INTERFACE (PINS 11, 12) | |||||||
VIL | Low Input Voltage | 0 | 0.3 VDD | V | |||
VIH | High Input Voltage | 0.7 VDD | VDD | V | |||
IIN | Input Current | VIN between 0.1 VDD and 0.9 VDD | −10 | +10 | μA | ||
IOL | Low Output Sink Current | VOL = 0 V or 0.4 V | 3 | mA | |||
STATUS FLAG OUTPUTS (PIN 16, 17) | |||||||
VOL | Low Output Voltage | IOUT = +10 mA | 0.4 | V | |||
VOH | High Output Voltage | IOUT = −10 mA | VDD −0.4V | V | |||
TOP OF FRAME OUTPUT (PIN 25) | |||||||
VOL | Low Output Voltage | IOUT = +10 mA | 0.4 | V | |||
VOH | High Output Voltage | IOUT = −10 mA | VDD −0.4V | V | |||
IOZ | Output Hi-Z Leakage Current | TOF output in Hi-Z mode, output pin connected to VDD or GND | 0.4 | 10 | |μA| | ||
tR | Rise Time | 15-pF load | 1.5 | ns | |||
tF | Fall Time | 15-pF load | 1.5 | ns | |||
tD_TOF | TOF Output Delay Time (5) | Specified for any SD or HD format generated from 27-MHz TOF clock (6), outputs initialized (7), 15 pF load | 2 | ns | |||
CLOCK OUTPUTS (PINS 19, 20, 23, 24) | |||||||
JitterSD | 27-MHz TIE Peak-to-Peak Output Jitter (8) | HD_CLK = Hi-Z | 23 | ps | |||
HD_CLK = 74.176 MHz | 40 | ps | |||||
67.5-MHz TIE Peak-to-Peak Output Jitter (8) | HD_CLK = Hi-Z | 40 | ps | ||||
HD_CLK = 74.176 MHz | 50 | ps | |||||
JitterHD | 74.176-MHz TIE Peak-to-Peak Output Jitter (8) | SD_CLK = Hi-Z | 55 | ps | |||
SD_CLK = 27 MHz | 65 | ps | |||||
74.25-MHz TIE Peak-to-Peak Output Jitter (8) | SD_CLK = Hi-Z | 40 | ps | ||||
SD_CLK = 27 MHz | 50 | ps | |||||
148.35-MHz TIE Peak-to-Peak Output Jitter (8) | SD_CLK = Hi-Z | 60 | ps | ||||
SD_CLK = 27 MHz | 70 | ps | |||||
148.5-MHz TIE Peak-to-Peak Output Jitter (8) | SD_CLK = Hi-Z | 45 | ps | ||||
SD_CLK = 27 MHz | 55 | ps | |||||
tD_SD | 27-MHz Output Delay Time (9) | SD_CLK = 27 MHz, Any valid output timing, outputs initialized (7) | 4 | ns | |||
67.5-MHz Output Delay Time (9) | SD_CLK = 67.5 MHz, 525i output timing (6), outputs initialized (7) | 6 | ns | ||||
tD_HD | 74.176-MHz Output Delay Time (10) | HD_CLK = 74.176 MHz, 1080i/59 output timing (6), outputs initialized (7) | 4.5 | ns | |||
74.25-MHz Output Delay Time (10) | HD_CLK = 74.25 MHz, 1080i/50 output timing (6), outputs initialized (7) | –0.6 | ns | ||||
148.35-MHz Output Delay Time (10) | HD_CLK = 148.35 MHz, 1080p/59 output timing (6), outputs initialized (7) | 1.5 | ns | ||||
148.5-MHz Output Delay Time (10) | HD_CLK = 148.5 MHz, 1080p/50 output timing (6), outputs initialized (7) | 4.5 | ns | ||||
VOD | Differential Signal Output Voltage (11) | 100-Ω differential load | 247 | 350 | 454 | mV | |
VOS | Common Signal Output Voltage (11) | 100-Ω differential load | 1.125 | 1.250 | 1.375 | V | |
|VOD| | |Change to VOD| for Complementary Output States (11) | 100-Ω differential load | 50 | |mV| | |||
|VOS| | |Change to VOS| for Complementary Output States (11) | 100-Ω differential load | 50 | |mV| | |||
IOS | Output Short Circuit Current | Differential clock output pins connected to GND | 24 | |mA| | |||
IOZ | Output Hi-Z Leakage Current | Output clock in Hi-Z mode, differential clock output pins connected to VDD or GND | 1 | 10 | |µA| |
GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1716, SD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1716, TOF_LPFM = 525, REF_LPFM = 525, TOF_OFFSET = 262; all other register settings are default |
GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 960, SD_FREQ = 0, HD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 960, TOF_LPFM = 1125, REF_LPFM = 1125, TOF_OFFSET = 562; all other register settings are default |
GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1728, SD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1728, TOF_LPFM = 625, REF_LPFM = 625, TOF_OFFSET = 312; all other register settings are default |
GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1000, SD_FREQ = 0, HD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1000, TOF_LPFM = 1125, REF_LPFM = 1125, TOF_OFFSET = 1124; all other register settings are default |