9.3.1 Analog Input Characteristics

The LMH2832 is a dual-channel device with two identical channels (A and B) that each have differential input pins (INP and INM) that denote the positive and negative inputs, respectively. The inputs are expected to be ac-coupled only, typically through a transformer or capacitor. The amplifier self-biases the input common-mode to mid-supply for the maximum input voltage range. The inputs of the LMH2832 can only be driven differentially. For single-ended input source applications, use a balun or fully differential amplifier (such as the LMH3401 or LMH5401) that can convert single-ended to differential signals before the LMH2832.

At maximum gain, the digital attenuator is set to 0 dB of attenuation, causing the input signal to be much larger than the output signal and forcing the maximum output voltage swing to be limited by the outputs of the device. However at minimum gain, the maximum voltage swing is limited by the inputs of the device because the attenuator causes the output voltage to be 9 dB lower than the input voltage. In minimum gain, the input voltage limits against the electrostatic discharge (ESD) devices before the output reaches the maximum swing limits. For linear operation, the input voltage must be kept within the maximum input voltage ratings described in the Electrical Characteristics table.

The input impedance of the LMH2832 is set by internal termination resistors to a nominal value of 150 Ω, differential. Process variations result in a range of values, as described in the Electrical Characteristics table. The input impedance is also affected by device parasitic effects at higher frequencies that cause the impedance to shift away from the nominal value.

9.3.2 Analog Output Characteristics

The LMH2832 has series, 10-Ω, on-chip resistors on each output to provide isolation from board parasitics that can cause instability. When designing a filter following the LMH2832, the filter source impedance calculation must include the two 10-Ω, on-chip resistors. Table 2 shows the calculated external source impedance values required for various matched filter loads.

9.3.3 Driving Low Insertion-Loss Filters

When driving high-speed ADCs, a filter is commonly driven with a matched impedance to the ADC. This impedance is matched by the amplifier by setting the combination of the output resistors to the same impedance as the ADC inputs. Impedance matching is often done to minimize any transmission reflections caused by the physical signal path. The drawback to using a matched impedance is that a voltage swing is required from the amplifier outputs that is twice the desired ADC input voltage swing, which can cause output voltage limitation issues.

To avoid using a matched impedance, a low insertion loss filter can be driven where there is little to no resistance added at the amplifier outputs. The amplifier outputs then only must swing to the value of the ADC full-scale input voltage, thus eliminating most of the potential amplifier output headroom issues. The requirements of this technique are that the amplifier must be able to provide enough current to the load of the ADC and that the path between the amplifier outputs and ADC inputs must be minimized to prevent any reflections.

9.3.4 Input Impedance Matching

The LMH2832 has a differential input impedance of 150 Ω that can be easily matched to single-ended, 50-Ω or 75-Ω systems using baluns. For a single-ended, 50-Ω input, a 1:3-Ω ratio balun can be used to create a 150-Ω differential source impedance to the device with a balun gain of 4.8 dB. For a single-ended, 75-Ω input, a 1:2-Ω ratio balun creates a 150-Ω differential source impedance to the device with a voltage gain of 3 dB.

9.3.5 Power-On Reset (POR)

The LMH2832 has a built-in, power-on-reset (POR) that sets the device registers to their default state (see the Register Maps section) on power-up. Note that the LMH2832 register information is lost when power is removed. When power is reapplied, the POR ensures that the device enters a default state. Power glitches (of sufficient duration) can also initiate the POR and return the device to a default state.

9.4.1 Power-Down (PD)

The device supports power-down control using an external power-down (PDx) pin or by writing a logic high to bit 6 of SPI register 2h (see the Register Maps section). The external PDx pins are active high; when left floating, the device defaults to an on condition resulting from the internal pulldown resistors that cause a logic low on the PDx pins. The device PDx thresholds are noted in the Electrical Characteristics table. The device consumes approximately 7 mA in power-down mode. Note that the SPI register contents are preserved in power-down mode.

9.4.2 Gain Control

The LMH2832 gain can be controlled from 30-dB gain (0-dB attenuation) to –9-dB gain in 1-dB steps by digitally programming the SPI register 2h; see the Register Maps section for more details.

9.5.1 Details of the Serial Interface

The LMH2832 has a set of internal registers that can be accessed by the serial interface formed by the CS (serial interface enable), SCLK (serial interface clock), SDI (serial interface input data), and SDO (serial interface read-back data) pins. Serially shifting bits into the device is enabled when CS is low. SDI serial data are latched at every SCLK rising edge when CS is active (low). The serial data are loaded into the register at every 16th SCLK rising edge when CS is low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active CS pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can function with SCLK frequencies from 25 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle. A summary of the LMH2832 SPI protocol is:

1. SPI-1.1 interface
2. Independent channel A, B attenuation programming (6-bit gain control)
3. SPI register contents are preserved in power-down mode
4. SPI-controlled power modes (3-bit control for eight options to step down the power)
5. Powered for the main 5-V power supply
6. 1.8-V logic

9.5.2 Timing Diagrams

Figure 44 and Figure 45 show timing diagrams for the SPI write and read bus cycles, respectively. Figure 46 shows an example timing diagram for a streaming write cycle and Figure 47 shows an example timing diagram for a streaming read cycle. Figure 48, Figure 49, Figure 50, and Figure 51 illustrate timing diagrams and requirements for the clock, data input, data output, and chip select, respectively. See the Timing Requirements: SPI table for SPI timing requirements.

Figure 44. SPI Write Bus Cycle Timing Diagram

Figure 45. SPI Read Bus Cycle Timing Diagram

Figure 46. SPI Streaming Write Example Timing Diagram

Figure 47. SPI Streaming Read Example Timing Diagram

Figure 48. SPI Clock Timing Diagram

Figure 49. SPI Data Input Timing Diagram

Figure 50. SPI Data Output Timing Diagrams

Figure 51. SPI Chip Select Timing Diagrams

Table 3. SPI Register Map

9.6.1 Register Descriptions

Exercising the SW reset function returns all registers to the default values of the respective channel.

9.6.2 Power-Down Control Register (address = 3)

9.6.3 Channel A RW0 Register (address = 4)

9.6.4 Channel A RW1 Register (address = 5)

9.6.5 Channel B RW0 Register (address = 6)

9.6.6 Channel B RW1 Register (address = 7)