JAJSFC0E December   2013  – January 2022 LMK00334

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements, Propagation Delay, and Output Skew
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Crystal Power Dissipation vs. RLIM
      2. 8.3.2 Clock Inputs
      3. 8.3.3 Clock Outputs
        1. 8.3.3.1 Reference Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 VCC and VCCO Power Supplies
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Driving the Clock Inputs
        2. 9.2.1.2 Crystal Interface
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Termination and Use of Clock Drivers
        2. 9.2.2.2 Termination for DC-Coupled Differential Operation
        3. 9.2.2.3 Termination for AC-Coupled Differential Operation
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Current Consumption and Power Dissipation Calculations
      1. 10.1.1 Power Dissipation Example: Worst-Case Dissipation
    2. 10.2 Power Supply Bypassing
      1. 10.2.1 Power Supply Ripple Rejection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Management
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-6B40FA7E-EFE4-49C5-ACFA-902F186C756D-low.gifFigure 5-1 RTV Package32-Pin WQFNTop View
Table 5-1 Pin Functions(3)
PIN I/O DESCRIPTION
NAME NO.
DAP DAP GND Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
CLKin_SEL0 13 I Clock input selection pins (2)
CLKin_SEL1 16 I Clock input selection pins (2)
CLKin0 14 I Universal clock input 0 (differential/single-ended)
CLKin0* 15 I Universal clock input 0 (differential/single-ended)
CLKin1 27 I Universal clock input 1 (differential/single-ended)
CLKin1* 26 I Universal clock input 1 (differential/single-ended)
CLKout_EN 9 I Bank A and Bank B low active output buffer enable. (2)
CLKoutA0 3 O Differential clock output A0.
CLKoutA0* 4 O Differential clock output A0.
CLKoutA1 6 O Differential clock output A1.
CLKoutA1* 7 O Differential clock output A1.
CLKoutB1 19 O Differential clock output B1.
CLKoutB1* 18 O Differential clock output B1.
CLKoutB0 22 O Differential clock output B0.
CLKoutB0* 21 O Differential clock output B0.
GND 1, 8 17, 24 GND Ground
NC 25 — Not connected internally. Pin may be floated, grounded, or otherwise tied to any potential within the Supply Voltage range stated in the Section 6.1.
OSCin 11 I Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock.
OSCout 12 O Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock.
REFout 29 O LVCMOS reference output. Enable output by pulling REFout_EN pin high.
REFout_EN 31 I REFout enable input. Enable signal is internally synchronized to selected clock input. (2)
VCC 10, 28, 32 PWR Power supply for Core and Input Buffer blocks. The VCC supply operates from 3.3 V. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCC pin.
VCCOA 2, 5 PWR Power supply for Bank A Output buffers. VCCOA operates from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (1)
VCCOB 20, 23 PWR Power supply for Bank B Output buffers. VCCOB operates from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (1)
VCCOC 30 PWR Power supply for REFout buffer. VCCOC operates from 3.3 V or 2.5 V. Bypass with a 0.1-µF, low-ESR capacitor placed very close to each VCCO pin. (1)
(1) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type.
(2) CMOS control input with internal pulldown resistor.
(3) Any unused output pins should be left floating with minimum copper length (see note in Section 8.3.3), or properly terminated if connected to a transmission line, or disabled/Hi-Z if possible. See Section 8.3.3 for output configuration and Section 9.2.2.1 for output interface and termination techniques.