JAJSFC0 データシート

JAJSFC0E December 2013 – January 2022 LMK00334

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RTV|32
- MPQF166B

サーマルパッド・メカニカル・データ

RTV|32
- QFND448B

発注情報

6.5 Electrical Characteristics

Unless otherwise specified: V_CC = 3.3 V ± 5%, V_CCO = 3.3 V ± 5%, 2.5 V ± 5%, –40°C ≤ T_A ≤ 85°C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent the most likely parametric norms at V_CC = 3.3 V, V_CCO = 3.3 V, T_A = 25°C, and at the Recommended Operation Conditions at the time of product characterization; because of this, typical values are not ensured. ⁽¹⁾

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION ⁽¹⁾
ICC_CORE	Core supply current, all outputs disabled	CLKinX selected			8.5	10.5	mA
ICC_CORE	Core supply current, all outputs disabled	OSCin selected			10	13.5	mA
ICC_HCSL					50	58.5	mA
ICC_CMOS					3.5	5.5	mA
ICCO_HCSL	Additive output supply current, HCSL banks enabled	Includes output bank bias and load currents for both banks, R_T = 50 Ω on all outputs			65	81.5	mA
ICCO_CMOS	Additive output supply current, LVCMOS output enabled	200 MHz, C_L = 5 pF	V_CCO = 3.3 V ±5%		9	10	mA
ICCO_CMOS	Additive output supply current, LVCMOS output enabled	200 MHz, C_L = 5 pF	V_CCO = 2.5V ± 5%		7	8	mA
POWER SUPPLY RIPPLE REJECTION (PSRR)
PSRR_HCSL	Ripple-induced phase spur level⁽²⁾ Differential HCSL Output	156.25 MHz			–72		dBc
PSRR_HCSL	Ripple-induced phase spur level⁽²⁾ Differential HCSL Output	312.5 MHz			–63		dBc
CMOS CONTROL INPUTS (CLKin_SELn, CLKout_TYPEn, REFout_EN)
V_IH	High-level input voltage			1.6		V_CC	V
V_IL	Low-level input voltage			GND		0.4	V
I_IH	High-level input current	V_IH = V_CC, internal pulldown resistor				50	μA
I_IL	Low-level input current	V_IL = 0 V, internal pulldown resistor		–5	0.1		μA
CLOCK INPUTS (CLKin0/CLKin0, CLKin1/CLKin1)
f_CLKin	Input frequency range⁽⁸⁾	Functional up to 400 MHz Output frequency range and timing specified per output type (refer to LVCMOS output specifications)		DC		400	MHz
V_IHD	Differential input high voltage	CLKin driven differentially				Vcc	V
V_ILD	Differential input low voltage			GND			V
V_ID	Differential input voltage swing⁽³⁾			0.15		1.3	V
V_CMD	Differential input CMD common-mode voltage	V_ID = 150 mV		0.25		V_CC – 1.2	V
		V_ID = 350 mV		0.25		V_CC – 1.1
		V_ID = 800 mV		0.25		V_CC – 0.9
V_IH	Single-ended input IH high voltage	CLKinX driven single-ended (AC- or DC-coupled), CLKinX* AC-coupled to GND or externally biased within V_CM range				V_CC	V
V_IL	Single-ended input IL low voltage			GND			V
V_{I_SE}	Single-ended input voltage swing⁽⁸⁾			0.3		2	Vpp
V_CM	Single-ended input CM common-mode voltage			0.25		V_CC – 1.2	V
ISO_MUX	Mux isolation, CLKin0 to CLKin1	f_OFFSET > 50 kHz, P_CLKinX = 0 dBm	f_CLKin0 = 100 MHz		–84		dBc
			f_CLKin0 = 200 MHz		–82
			f_CLKin0 = 500 MHz		–71
			f_CLKin0 = 1000 MHz		–65
CRYSTAL INTERFACE (OSCin, OSCout)
F_CLK	External clock frequency range⁽⁸⁾	OSCin driven single-ended, OSCout floating				250	MHz
F_XTAL	Crystal frequency range	Fundamental mode crystal ESR ≤ 200 Ω (10 to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz)⁽⁴⁾		10		40	MHz
C_IN	OSCin input capacitance				1		pF
HCSL OUTPUTS (CLKoutAn/CLKoutAn, CLKoutBn/CLKoutBn)
f_CLKout	Output frequency range⁽⁸⁾	R_L = 50 Ω to GND, C_L ≤ 5 pF		DC		400	MHz
Jitter_{ADD_PCle}	Additive RMS phase jitter for PCIe 5.0⁽⁸⁾	PCIe Gen 5 filter	CLKin: 100 MHz, slew rate ≥ 0.5 V/ns		0.015	0.03	ps
Jitter_{ADD_PCle}	Additive RMS phase jitter for PCIe 4.0⁽⁸⁾	PCIe Gen 4, PLL BW = 2–5 MHz, CDR = 10 MHz	CLKin: 100 MHz, slew rate ≥ 1.8 V/ns		0.03	0.05	ps
Jitter_{ADD_PCle}	Additive RMS phase jitter for PCIe 3.0⁽⁸⁾	PCIe Gen 3, PLL BW = 2–5 MHz, CDR = 10 MHz	CLKin: 100 MHz, slew rate ≥ 0.6 V/ns		0.03	0.15	ps
Jitter_ADD	Additive RMS jitter integration bandwidth 12 MHz to 20 MHz⁽⁵⁾	V_CCO = 3.3 V, R_T = 50 Ω to GND	CLKin: 100 MHz, slew rate ≥ 3 V/ns		77		fs
Noise Floor	Noise floor f_OFFSET ≥ 10 MHz⁽⁶⁾⁽⁷⁾	V_CCO = 3.3 V, R_T = 50 Ω to GND	CLKin: 100 MHz, slew rate ≥ 3 V/ns		–161.3		dBc/Hz
DUTY	Duty cycle⁽⁸⁾	50% input clock duty cycle		45%		55%
V_OH	Output high voltage	T_A = 25°C, DC measurement, R_T = 50 Ω to GND		520	810	920	mV
V_OH	Output high voltage			–150	0.5	150	mV
V_OL	Output low voltage			–150	0.5	150	mV
V_CROSS	Absolute crossing voltage⁽⁸⁾⁽⁹⁾	R_L = 50 Ω to GND, C_L ≤ 5 pF		250	350	460	mV
V_CROSS	Absolute crossing voltage⁽⁸⁾⁽⁹⁾					140	mV
ΔV_CROSS	Total variation of V_CROSS⁽⁸⁾⁽⁹⁾					140	mV
t_R	Output rise time 20% to 80%⁽⁹⁾⁽¹²⁾	250 MHz, uniform transmission line up to 10 in. with 50-Ω characteristic impedance, R_L = 50 Ω to GND, C_L ≤ 5 pF			225	400	ps
t_F	Output fall time 80% to 20%⁽⁹⁾⁽¹²⁾				225	400	ps
LVCMOS OUTPUT (REFout)
f_CLKout	Output frequency range⁽⁸⁾	C_L ≤ 5 pF		DC		250	MHz
Jitter_ADD	Additive RMS jitter integration bandwidth 1 MHz to 20 MHz⁽⁵⁾	V_CCO = 3.3 V, C_L ≤ 5 pF	100 MHz, input slew rate ≥ 3 V/ns		95		fs
Noise Floor	Noise floor f_OFFSET ≥ 10 MHz⁽⁶⁾⁽⁷⁾	V_CCO = 3.3 V, C_L ≤ 5 pF	100 MHz, input slew rate ≥ 3 V/ns		–159.3		dBc/Hz
DUTY	Duty cycle⁽⁸⁾	50% input clock duty cycle		45%		55%
V_OH	Output high voltage	1-mA load		V_CCO – 0.1			V
V_OL	Output low voltage	1-mA load				0.1	V
I_OH	Output high current (source)	V_O = V_CCO / 2	V_CCO = 3.3 V		28		mA
			V_CCO = 2.5 V		20		mA
			V_CCO = 3.3 V		28		mA
			V_CCO = 2.5 V		20
I_OL	Output low current (sink)		V_CCO = 2.5 V		20
t_R	Output rise time 20% to 80%⁽⁹⁾⁽¹²⁾	250 MHz, uniform transmission line up to 10 in. with 50-Ω characteristic impedance, R_L = 50 Ω to GND, C_L ≤ 5 pF			225	400	ps
t_F	Output fall time 80% to 20%⁽¹⁰⁾⁽¹²⁾				225	400	ps
t_EN	Output enable time⁽¹⁰⁾	C_L ≤ 5 pF				3	cycles
t_DIS	Output disable time⁽¹⁰⁾	C_L ≤ 5 pF				3	cycles

(1) See Section 10 and Section 11.3 for more information on current consumption and power dissipation calculations.

(2) Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone sinusoidal signal (ripple) is injected onto the V_CCO supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 × 10(^PSRR / 20)) / (π × f_CLK) ] × 1E12

(3) See Section 7.1 for definition of V_ID and V_OD voltages.

(4) The ESR requirements stated must be met to ensure that the oscillator circuitry has no start-up issues. However, lower ESR values for the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Section 9.2.1.2 for crystal drive level considerations.

(5) For the 100-MHz and 156.25-MHz clock input conditions, Additive RMS Jitter (J_ADD) is calculated using Method #1: J_ADD = SQRT(J_OUT² - J_SOURCE²), where J_OUT is the total RMS jitter measured at the output driver and J_SOURCE is the RMS jitter of the clock source applied to CLKin. For the 625-MHz clock input condition, Additive RMS Jitter is approximated using Method #2: J_ADD = SQRT(2 × 10^dBc/10) / (2 × π × f_CLK), where dBc is the phase noise power of the Output Noise Floor integrated from 12-kHz to 20-MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10 × log₁₀(20 MHz – 12 kHz).

(6) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.

(7) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common-mode noise rejection. However, TI recommends using the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs.

(8) Specification is ensured by characterization and is not tested in production.

(9) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.

(10) Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement.

(11) Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same supply voltage and temperature conditions.

(12) Parameter is specified by design, not tested in production.