JAJSMK7C December   2013  – July 2021 LMK00338

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Crystal Power Dissipation vs. RLIM
      2. 8.3.2 Clock Inputs
      3. 8.3.3 Clock Outputs
        1. 8.3.3.1 Reference Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 VCC and VCCO Power Supplies
  9. 9 Power Supply Recommendations
    1. 9.1 Current Consumption and Power Dissipation Calculations
      1. 9.1.1 Power Dissipation Example: Worst-Case Dissipation
    2. 9.2 Power Supply Bypassing
      1. 9.2.1 Power Supply Ripple Rejection
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Unless otherwise specified: VCC = 3.3 V ± 5%, VCCO = 3.3 V ± 5%, 2.5 V ± 5%, –40°C ≤ TA ≤ 85°C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at VCC = 3.3 V, VCCO = 3.3 V, TA = 25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION(3)
ICC_CORE Core supply current, all outputs disabled CLKinX selected 8.5 10.5 mA
OSCin selected 10 13.5 mA
ICC_HCSL 31 38.5 mA
ICC_CMOS 3.5 5.5 mA
ICCO_HCSL Additive output supply current, HCSL banks enabled Includes Output Bank Bias and Load Currents for both banks, RT = 50 Ω on all outputs in bank 68 84 mA
ICCO_CMOS Additive output supply current, LVCMOS output enabled 200 MHz,
CL = 5 pF		 VCCO = 3.3 V ±5% 9 10 mA
VCCO = 2.5V ± 5% 7 8 mA
POWER SUPPLY RIPPLE REJECTION (PSRR)
PSRRHCSL Ripple-induced phase spur level(4)
Differential HCSL output		 156.25 MHz –72 dBc
312.5 MHz –63
CMOS CONTROL INPUTS (CLKin_SELn, CLKout_TYPEn, REFout_EN)
VIH High-level input voltage 1.6 Vcc V
VIL Low-level input voltage GND 0.4 V
IIH High-level input current VIH = VCC, internal pulldown resistor 50 μA
IIL Low-level input current VIL = 0 V, internal pulldown resistor –5 0.1 μA
CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*)
fCLKin Input frequency range(10) Functional up to 400 MHz
Output frequency range and timing specified per output type (refer to HCSL, LVCMOS output specifications)		 DC 400 MHz
VIHD Differential input high voltage CLKin driven differentially VCC V
VILD Differential input low voltage GND V
VID Differential input voltage swing(5) 0.15 1.3 V
VCMD Differential input CMD common-mode voltage VID = 150 mV 0.25 VCC – 1.2 V
VID = 350 mV 0.25 VCC – 1.1
VID = 800 mV 0.25 VCC – 0.9
VIH Single-ended input IH high voltage CLKinX driven single-ended (AC- or DC-coupled), CLKinX* AC-coupled to GND or externally biased within VCM range VCC V
VIL Single-ended input IL low voltage GND V
VI_SE Single-ended input voltage swing(14) 0.3 2 Vpp
VCM Single-ended input CM common-mode voltage 0.25 VCC – 1.2 V
ISOMUX Mux isolation, CLKin0 to CLKin1 fOFFSET > 50 kHz,
PCLKinX = 0 dBm		 fCLKin0 = 100 MHz –84 dBc
fCLKin0 = 200 MHz –82
fCLKin0 = 500 MHz –71
fCLKin0 = 1000 MHz –65
CRYSTAL INTERFACE (OSCin, OSCout)
FCLK External clock frequency range(10) OSCin driven single-ended, OSCout floating 250 MHz
FXTAL Crystal frequency range Fundamental mode crystal ESR ≤ 200 Ω (10 to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz)(6) 10 40 MHz
CIN OSCin input capacitance 1 pF
HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKout Output frequency range(10) RL = 50 Ω to GND, CL ≤ 5 pF DC 400 MHz
JitterADD_PCle Additive RMS phase jitter for PCIe 5.0(10) PCIe Gen 5 filter CLKin: 100 MHz,
Slew rate ≥ 0.5 V/ns

0.015

 0.03

ps
JitterADD_PCle Additive RMS phase jitter for PCIe 4.0(10) PCIe Gen 4,
PLL BW = 2–5 MHz,
CDR = 10 MHz		 CLKin: 100 MHz,
Slew rate ≥ 1.8 V/ns		 0.03 0.05 ps
JitterADD_PCle Additive RMS phase jitter for PCIe 3.0(10) PCIe Gen 3,
PLL BW = 2–5 MHz,
CDR = 10 MHz		 CLKin: 100 MHz,
Slew rate ≥ 0.6 V/ns		 0.03 0.15 ps
JitterADD Additive RMS jitter integration bandwidth to 20 MHz(8)(9) VCCO = 3.3 V,
RT = 50 Ω to GND		 CLKin: 100 MHz,
Slew rate ≥ 3 V/ns		 77 fs
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns		 86
Noise Floor Noise floor fOFFSET ≥ 10 MHz(8)(9) VCCO = 3.3 V,
RT = 50 Ω to GND		 CLKin: 100 MHz,
Slew rate ≥ 3 V/ns		 –161.3 dBc/Hz
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns		 –156.3
DUTY Duty cycle(10) 50% input clock duty cycle 45% 55%
VOH Output high voltage TA = 25°C, DC measurement,
RT = 50 Ω to GND		 520 810 920 mV
–150 0.5 150 mV
VOL Output low voltage
VCROSS Absolute crossing voltage(10)(11) RL = 50 Ω to GND,
CL ≤ 5 pF		 160 350 460 mV
140 mV
ΔVCROSS Total variation of VCROSS
tR Output rise time 20% to 80%(11)(14) 250 MHz, uniform transmission line up to 10 in.
with 50-Ω characteristic impedance,
RL = 50 Ω to GND, CL ≤ 5 pF		 300 500 ps
tF Output fall time 80% to 20%(11)(14) 300 500 ps
LVCMOS OUTPUT (REFout)
fCLKout Output frequency range(10) CL ≤ 5 pF DC 250 MHz
JitterADD Additive RMS jitter integration bandwidth 1 MHz to 20 MHz(7) VCCO = 3.3 V,
CL ≤ 5 pF		 100 MHz,
Input slew rate ≥ 3 V/ns		 95 fs
Noise Floor Noise floor fOFFSET ≥ 10 MHz(8)(9) VCCO = 3.3 V,
CL ≤ 5 pF		 100 MHz,
Input slew rate ≥ 3 V/ns		 –159.3 dBc/Hz
DUTY Duty cycle(10) 50% input clock duty cycle 45% 55%
VOH Output high voltage 1-mA load VCCO – 0.1 V
VOL Output low voltage 0.1 V
IOH Output high current (source) VO = VCCO / 2 VCCO = 3.3 V 28 mA
VCCO = 2.5 V 20
VCCO = 3.3 V 28 mA
VCCO = 2.5 V 20
IOL Output low current (sink)
tR Output rise time 20% to 80%(11)(14) 250 MHz, uniform transmission line up to 10 in. with 50-Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF 225 400 ps
tF Output fall time 80% to 20%(11)(14) 225 400 ps
tEN Output enable time(12) CL ≤ 5 pF 3 cycles
tDIS Output disable time(12) 3 cycles
PROPAGATION DELAY and OUTPUT SKEW
tPD_HCSL Propagation delay CLKin-to-HCSL(11)(14) RT = 50 Ω to GND,
CL ≤ 5 pF		 295 590 885 ps
tPD_CMOS Propagation delay CLKin-to-LVCMOS(11)(14) CL ≤ 5 pF VCCO = 3.3 V 900 1475 2300 ps
VCCO = 2.5 V 1000 1550 2700
tSK(O) Output skew(10)(11)(13) Skew specified between any two CLKouts.
Load conditions are the same as propagation delay specifications.		 30 50 ps
tSK(PP) Part-to-part output skew
HCSL(11)(14)(13)		 80 120 ps
(1) The output supply voltages/pins (VCCOA, VCCOB, and VCCOC) will be referred to generally as VCCO when no distinction is needed, or when the output supply can be inferred by the output bank/type.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and notes. Typical specifications are estimations only and are not ensured.
(3) See Section 9 for more information on current consumption and power dissipation calculations.
(4) Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone sinusoidal signal (ripple) is injected onto the VCCO supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 × 10(PSRR / 20)) / (π × fCLK) ] × 1E12
(5) See Section 7.1 for definition of VID and VOD voltages.
(6) The ESR requirements stated must be met to ensure that the oscillator circuitry has no start-up issues. However, lower ESR values for the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Section 9.2.1.2 for crystal drive level considerations.
(7) For the 100-MHz and 156.25-MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2 – JSOURCE2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to CLKin. For the 625-MHz clock input condition, additive RMS jitter is approximated using Method #2: JADD = SQRT(2 × 10dBc/10) / (2 × π × fCLK), where dBc is the phase noise power of the output noise floor integrated from 1-MHz to 20-MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10 × log10(20 MHz – 1 MHz). The additive RMS jitter was approximated for 625 MHz using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer to the Noise Floor vs. CLKin Slew Rate and RMS Jitter vs. CLKin Slew Rate plots in Section 6.6.
(8) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.
(9) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) is less susceptible to degradation in noise floor at lower slew rates due to its common-mode noise rejection. However, TI recommends using the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs.
(10) Specification is ensured by characterization and is not tested in production.
(11) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.
(12) Output enable time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly, output disable time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement.
(13) Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same supply voltage and temperature conditions.
(14) Parameter is specified by design, not tested in production.