When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:
- Transmission line theory should be followed for good impedance matching to prevent reflections.
- Clock drivers should be presented with the proper loads.
- HCSL drivers are switched current outputs and require a DC path to ground through 50-Ω termination.
- Receivers should be presented with a signal biased to their specified DC bias level (common-mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level; in this case, the signal should normally be AC-coupled.