To use dynamic digital delay synchronization qualification set SYNC1_QUAL = 3. This causes the SYNC pulse to be qualified by a clock output so that the SYNC event occurs after a specified time from a clock output transition. This allows the relative adjustment of clock output phase in real-time with no or minimum interruption of clock outputs. Hence the term dynamic digital delay.

Note that changing the phase of a clock output requires momentarily altering in the rate of change of the clock output phase and therefore by definition results in a frequency distortion of the signal.

Without qualifying the SYNC with an output clock, the newly synchronized clocks would have a random and unknown digital delay (or phase) with respect to clock outputs not currently being synchronized. Only CLKout12 can be used as a qualifying clock.

Relative Dynamic Digital Delay

When the qualifying clock digital delay is being adjusted, because the qualifying clock and the adjusted clock are the same, then a relative dynamic digital delay adjust is performed. Clocks with NO_SYNC_CLKoutX_Y = 1 are defined as clocks not being adjusted. These clocks operate without interruption.

SYNC and Minimum Step Size

The minimum step size adjustment for digital delay is half a clock distribution path cycle. This is achieved by using the CLKout12_13_HS bit. The CLKout12_13_HS bit change effect is immediate without the need for SYNC. To shift digital delay using CLKout12_13_DDLY, a SYNC signal must be generated for the change to take effect.

Programming Overview

To dynamically adjust the digital delay with respect to an existing clock output the device should be programmed as follows:

• Set SYNC1_QUAL = 3 for clock output qualification.
• Set NO_SYNC_CLKout12_13 = 0 to enable synchronization on CLKout12 and CLKout13.
• Set CLKout12_ADLY_SEL = 0.
• Set NO_SYNC_CLKoutX_Y = 1 for the output clocks, except CLKout12 and CLKout13, that will continue to operate during the SYNC event. There is no interruption of output on these clocks.
• The SYNC_EN_AUTO bit may be set to cause a SYNC event to begin when register R4 is programmed. The auto SYNC feature is a convenience since it does not require the application to manually assert SYNC by toggling the SYNC_POL_INV bit or the SYNC pin when changing digital delay.

Internal Dynamic Digital Delay Timing

Once SYNC is qualified by an output clo