JAJSGV2D January   2012  – September 2021 LMK01801

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Functional Configurations
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Thermal Information
    4. 7.4 Electrical Characteristics
    5. 7.5 Serial MICROWIRE Timing Diagram
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  High-Speed Clock Inputs (CLKin0/CLKin0* and CLKin1/CLKin1*)
      2. 9.3.2  Clock Distribution
      3. 9.3.3  Small Divider (1 to 8)
      4. 9.3.4  Large Divider (1 to 1045)
      5. 9.3.5  CLKout Analog Delay
      6. 9.3.6  CLKout0 to CLKout11 Digital Delay
      7. 9.3.7  CLKout12 and CLKout13 Digital Delay
      8. 9.3.8  Programmable Outputs
      9. 9.3.9  Clock Output Synchronization
      10. 9.3.10 Default Clock Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Programmable Mode
      2. 9.4.2 Pin Control Mode
      3. 9.4.3 Inputs / Outputs
        1. 9.4.3.1 CLKin0 and CLKin1
      4. 9.4.4 Input and Output Dividers
      5. 9.4.5 Fixed Digital Delay
        1. 9.4.5.1 Fixed Digital Delay - Example
      6. 9.4.6 Clock Output Synchronization (SYNC)
        1. 9.4.6.1 Dynamically Programming Digital Delay
          1. 9.4.6.1.1 Relative Dynamic Digital Delay
          2. 9.4.6.1.2 Relative Dynamic Digital Delay - Example
    5. 9.5 Programming
      1. 9.5.1 Recommended Programming Sequence
        1. 9.5.1.1 Overview
    6. 9.6 Register Map
      1. 9.6.1 Default Device Register Settings After Power On/Reset
      2. 9.6.2 Register R0
        1. 9.6.2.1 RESET
        2. 9.6.2.2 POWERDOWN
        3. 9.6.2.3 CLKoutX_Y_PD
          1. 9.6.2.3.1 CLKinX_BUF_TYPE
          2. 9.6.2.3.2 CLKinX_DIV
          3. 9.6.2.3.3 CLKinX_MUX
      3. 9.6.3 Register R1 and R2
        1. 9.6.3.1 CLKoutX_TYPE
      4. 9.6.4 Register R3
        1. 9.6.4.1 CLKout12_13_ADLY
        2. 9.6.4.2 CLKout12_13_HS, Digital Delay Half Shift
        3. 9.6.4.3 SYNC1_QUAL
        4. 9.6.4.4 SYNCX_POL_INV
        5. 9.6.4.5 NO_SYNC_CLKoutX_Y
        6. 9.6.4.6 CLKoutX_Y_OFFSET_PD
        7. 9.6.4.7 SYNCX_FAST
        8. 9.6.4.8 SYNCX_AUTO
      5. 9.6.5 Register R4
        1. 9.6.5.1 CLKout12_13_DDLY, Clock Channel Digital Delay
      6. 9.6.6 Register R5
        1. 9.6.6.1 CLKout12_ADLY_SEL[13], CLKout13_ADLY_SEL[14], Select Analog Delay
        2. 9.6.6.2 CLKoutX_Y_DIV Clock Output Divide
      7. 9.6.7 Register 15
        1. 9.6.7.1 uWireLock
  10. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Detailed Design Procedure
        1. 10.1.1.1 Driving CLKin Inputs
          1. 10.1.1.1.1 Driving CLKin Pins With a Differential Source
          2. 10.1.1.1.2 Driving CLKin Pins With a Single-Ended Source
        2. 10.1.1.2 Termination and Use of Clock Output (Drivers)
          1. 10.1.1.2.1 Termination for DC-Coupled Differential Operation
          2. 10.1.1.2.2 Termination for AC-Coupled Differential Operation
          3. 10.1.1.2.3 Termination for Single-Ended Operation
  11. 11Power Supply Recommendations
    1. 11.1 Current Consumption
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Pin Connection Recommendations
        1. 12.1.1.1 Vcc Pins and Decoupling
        2. 12.1.1.2 Unused clock outputs
        3. 12.1.1.3 Unused clock inputs
        4. 12.1.1.4 Unused GPIO (CLKoutTYPE_X)
        5. 12.1.1.5 Bias
        6. 12.1.1.6 In MICROWIRE Mode
    2. 12.2 Thermal Management
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.1 Current Consumption

Note:

Assuming θJA = 25.8°C/W, the total power dissipated on chip must be less than (125°C - 85°C) / 25.8°C/W = 1.5 W to ensure a junction temperature less than 145°C.

Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.20.

From Table 11-1 the current consumption can be calculated for any configuration.

For example, the current for the entire device with 1 LVDS (CLKout0) and 1 LVPECL 1600 mVpp /w 240 Ω emitter resistors (CLKout1) output active with a clock output divide = 1, and no other features enabled can be calculated by adding the following blocks:

  • Core Current
  • Clock Buffer
  • One LVDS Output Buffer Current
  • Bank A
  • Output Divider Buffer Current
  • LVPECL 1600 mVpp buffer /w 240 Ω emitter resistors

Since there will be one LVPECL output drawing emitter current, this means some of the power from the current draw of the device is dissipated in the external emitter resistors which doesn’t add to the power dissipation budget for the device but is important for LDO ICC calculations.

For total current consumption of the device add up the significant functional blocks. In this example 92 mA =

  • 1 mA (core current)
  • 22 mA (Bank A current)
  • 15 mA (Output Buffer current)
  • 21 mA (Output Divider current)
  • 9 mA (LVDS output current)
  • 24 mA (LVPECL 1600 mVpp buffer /w 240 Ω emitter resistors)

Once the total current consumption has been calculated, power dissipated by the device can be calculated. The power dissipation of the device is equal to the total current entering the device multiplied by the voltage at the device minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter resistors are connected to the LVPECL outputs, this power will be 0 watts. Continuing the output with 240 Ω emitter resistors. Total IC power = 275.1 mW = 3.3 V * 95 mA -28.5 mW.

Table 11-1 Typical Current Consumption for Selected Functional Blocks
(TA = 25°C, VCC = 3.3 V)
BlockConditionTypical ICC (mA)Power dissipated in device (mW)Power dissipated externally (mW)
(1)
Core
CoreAll outputs and dividers off13.3-
BankBank AAt least on output enabled2272.6-
Bank BAt least on output enabled2582.5-
BuffersCLKout0 to CLKout3On when any on output in the group is enabled1549.5-
CLKout4 to CLKout7-
CLKout8 to CLKout11-
CLKout12 to CLKout13-
Output DividerCLKout0 to CLKout11Divide = 12169.3-
Divide = 2 to 824.279.8-
CLKout12 and CLKout13Divide = 1 to 25 and DDLY = 1 to 121549.5-
Divide = 26 to 1045 or DDLY > 1319.163.0-
Input DividerBank ADivide = 2 to 8929.7-
Bank BDivide = 2 to 8-
Analog DelayAnalog Delay ValueCLKout12_13_ADLY = 0 to 33.411.2-
CLKout12_13_ADLY = 4 to 73.812.5-
CLKout12_13_ADLY = 8 to 114.213.9-
CLKout12_13_ADLY = 12 to 154.715.5-
CLKout12_13_ADLY = 16 to 235.217.2-
When only one, CLKout12 or CLKout13, have Analog Delay Selected.2.89.2-
Clock Output Buffers
LVDSCLkout0 to CLKout11; 100 Ω differential termination929.7-
CLkout12 to CLKout13; 100 Ω differential termination1446.2-
LVPECLCLkout0 to CLKout11; LVPECL 1600 mVpp,
AC coupled using 240 Ω emitter resistors		2479.228.5
CLkout12 to CLKout13; LVPECL 1600 mVpp,
AC coupled using 240 Ω emitter resistors		29.597.328.5
LVCMOSLVCMOS Pair, CLKout4 to CLKout11,
(CLKoutX_TYPE = 6 - 10), CL = 5 pF		10 MHz18.661.4-
50 MHz23.176.2-
150 MHz31.7104.6-
LVCMOS Pair, CLKout12 and CLKout13,
(CLKoutX_TYPE = 6 - 10), CL = 5 pF		10 MHz24.781.51-
50 MHz30.3100-
150 MHz42.0138.6-
LVCMOS Single, CLKout4 to CLKout11,
(CLKoutX_TYPE=11 - 13), CL = 5 pF		10 MHz9.732-
50 MHz10.835.6-
150 MHz13.544.5-
LVCMOS Single, CLKout12 and CLKout13,
(CLKoutX_TYPE= 11 - 13), CL = 5 pF		10 MHz1549.5-
50 MHz17.557.7-
150 MHz22.875.2-
(1) Power is dissipated externally in LVPECL emitter resistors. The externally dissipated power is calculated as twice the DC voltage level of one LVPECL clock output pin squared over the emitter resistance. That is to say power dissipated in emitter resistors = 2 * Vem2/Rem