JAJSFA5E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
The DEV_CTL register holds the control functions described in the following table.
Bit # | Field | Type | Reset | EEPROM | Description | |
---|---|---|---|---|---|---|
[7] | RESETN_SW | RW | 1 | N | Software Reset ALL functions (active low). Writing a 0 will cause the device to return to its power-up state apart from the I2C registers and the configuration controller. The configuration controller is excluded to prevent a re-transfer of EEPROM data to on-chip registers. | |
[6] | SYNCN_SW | RW | 1 | N | Software SYNC Assertion (active low). Writing a 0 to this bit is equivalent to asserting the GPIO0 pin. | |
[5] | RSRVD | - | - | N | Reserved. | |
[4] | SYNC_AUTO | RW | 1 | Y | Automatic Synchronization at startup. When SYNC_AUTO is 1 at device startup a synchronization sequence is initiated automatically after PLL lock has been achieved. | |
[3] | SYNC_MUTE | RW | 1 | Y | Synchronization Mute Control. The SYNC_MUTE field determines whether or not the output drivers are muted during a Synchronization event. | |
SYNC_MUTE | SYNC Mute Behaviour | |||||
0 | Do not mute any outputs during SYNC | |||||
1 | Mute all outputs during SYNC | |||||
[2] | AONAFTERLOCK | RW | 0 | Y | Always On Clock behaviour after Lock. If AONAFTERLOCK is 0 then the system clock is switched from the Always On Clock to the VCO Clock after lock and the Always On Clock oscillator is disabled. If AONAFTERLOCK is 1 then the Always on Clock will remain as the digital system clock regardless of the PLL Lock state. TI recommends setting the AONAFTERLOCK to 1. | |
[1] | RSRVD | RW | 0 | Y | Reserved. | |
[0] | AUTOSTRT | RW | 1 | Y | Autostart. If AUTOSTRT is set to 1 the device will automatically attempt to achieve lock and enable outputs after a device reset. A device reset can be triggered by the power-on-reset, RESETn pin or by writing to the RESETN_SW bit. If AUTOSTRT is 0 then the device will halt after the configuration phase, a subsequent write to set the AUTOSTRT bit to 1 will trigger the PLL Lock sequence. |