JAJSFA5E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
The PWDN register is described in the following table.
Bit # | Field | Type | Reset | EEPROM | Description |
---|---|---|---|---|---|
[7] | RSRVD | - | - | N | Reserved. |
[6] | CMOSCHPWDN | RW | 0 | Y | CMOS Output Channel Powerdown. |
[5] | CH7PWDN | RW | 0 | Y | Output Channel 7 Powerdown. When CH7PWDN is 1, the MUX and divider of channel 7 will be disabled. To shut down entire output path (output MUX, divider and buffer), R43[5:4] should be set to 0x0 irrespective of R30.5. |
[4] | CH6PWDN | RW | 0 | Y | Output Channel 6 Powerdown. When CH6PWDN is 1, the MUX and divider of channel 6 will be disabled. To shut down entire output path (output MUX, divider and buffer), R41[5:4] should be set to 0x0 irrespective of R30.4. |
[3] | CH5PWDN | RW | 0 | Y | Output Channel 5 Powerdown. When CH5PWDN is 1, the MUX and divider of channel 5 will be disabled. To shut down entire output path (output MUX, divider and buffer), R39[5:4] should be set to 0x0 irrespective of R30.3. |
[2] | CH4PWDN | RW | 0 | Y | Output Channel 4 Powerdown. When CH4PWDN is 1, the MUX and divider of channel 4 will be disabled. To shut down entire output path (output MUX, divider and buffer), R37[5:4] should be set to 0x0 irrespective of R30.2. |
[1] | CH23PWDN | RW | 0 | Y | Output Channel 23 Powerdown. When CH23PWDN is 1, the MUX and divider of channels 2 and 3 will be disabled. To shut down entire output paths (output MUX, divider and buffers), R35[6:5] and R34[6:5] should be set to 0x0 irrespective of R30.1. |
[0] | CH01PWDN | RW | 0 | Y | Output Channel 01 Powerdown. When CH01PWDN is 1, the MUX and divider of channels 0 and 1 will be disabled. To shut down entire output paths (output MUX, divider and buffers), R32[6:5] and R31[6:5] should be set to 0x0 irrespective of R30.0. |