JAJSFA5E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
The OUTCTL_2 register provides control over Output 2.
Bit # | Field | Type | Reset | EEPROM | Description | ||
---|---|---|---|---|---|---|---|
[7] | RSRVD | RW | 1 | Y | Reserved. TI recommends setting it to 0. | ||
[6:5] | OUT_2_SEL[1:0] | RW | 0x1 | Y | Channel 2 Output Driver Format Select. The OUT_2_SEL field controls the Channel 2 Output Driver as shown below. | ||
OUT_2_SEL | OUTPUT OPERATION | ||||||
0 (0x0) | Disabled | ||||||
1 (0x1) | AC-LVDS/AC-CML/AC-LVPECL | ||||||
2 (0x2) | HCSL | ||||||
3 (0x3) | LVCMOS | ||||||
[4:3] | OUT_2_MODE1[1:0] | RW | 0x2 | Y | Channel 2 Output Driver Mode1 Select. | ||
OUT_2_MODE1 | Diff-Mode, Itail | CMOS-Mode, Out_P | |||||
0 (0x0) | 4 mA (AC-LVDS) | Powerdown, tristate | |||||
1 (0x1) | 6 mA (AC-CML) | Powerdown, low | |||||
2 (0x2) | 8 mA (AC-LVPECL) | Powerup, negative polarity | |||||
3 (0x3) | 16 mA (HCSL) or 8 mA (AC-LVPECL) | Powerup, positive polarity | |||||
[2:1] | OUT_2_MODE2[1:0] | RW | 0x0 | Y | Channel 2 Output Driver Mode2 Select. | ||
OUT_2_MODE2 | Diff-Mode, Rload in HCSL mode | CMOS=Mode, Out_N | |||||
0 (0x0) | Tristate | Powerdown, tristate | |||||
1 (0x1) | 50 Ω | Powerdown, low | |||||
2 (0x2) | 100 Ω | Powerup, negative polarity | |||||
3 (0x3) | 200 Ω | Powerup, positive polarity | |||||
[0] | RSRVD | - | - | N | Reserved. |