JAJSFA5E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
The PLL_CALCTRL0 register is described in the following table.
Bit # | Field | Type | Reset | EEPROM | Description | |
---|---|---|---|---|---|---|
[7:4] | RSRVD | - | - | N | Reserved. | |
[3:2] | PLL_CLSDWAIT[1:0] | RW | 0x0 | Y | Closed Loop Wait Period. The CLSDWAIT field sets the closed loop wait period, in periods of the always on clock as follows. Use 0x1 for clock generator mode (> 10 kHz loop bandwidth) and 0x3 for jitter cleaner mode (< 1 kHz loop bandwidth). | |
CLSDWAIT | Analog closed loop VCO stabilization time | |||||
0 (0x0) | 30 µs | |||||
1 (0x1) | 300 µs | |||||
2 (0x2) | 30 ms | |||||
3 (0x3) | 300 ms | |||||
[1:0] | PLL_VCOWAIT[1:0] | RW | 0x1 | Y | VCO Wait Period. Use 0x1 for all modes. | |
VCOWAIT | VCO stabilization time | |||||
0 (0x0) | 20 µs | |||||
1 (0x1) | 400 µs | |||||
2 (0x2) | 8000 µs | |||||
3 (0x3) | 200000 µs |