JAJSFA5E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
Before the outputs are enabled after power up, the LMK03318 goes through the initialization routine given in Table 20.
| Parameter | Definition | Duration | Comments |
|---|---|---|---|
| TPWR | Step 1: Power up ramp | Depends on customer supply ramp time | The POR monitor holds the device in power-down/reset until the core supply voltages reaches 2.72 V (min) to 2.95 V (max) and VDDO_01 reaches 1.7 V (min). |
| TXO | Step 2: XO startup (if crystal is used) | Depends on XTAL. Could be several ms; For TXC 25 MHz typical XTAL startup time measures 100 µs. | This step assumes PDN=1. The XTAL startup time is the time it takes for the XTAL to oscillate with sufficient amplitude. The LMK03318 has a built-in amplitude detection circuit, and halts the PLL lock sequence until the XTAL stage has sufficient swing. |
| TCAL-PLL | Step 3: Closed loop calibration period for PLL | Programmable cycles of internal 10 MHz oscillator. | This counter is needed for the PLL loop to stabilize. It can also be used to provide additional delay time for the selected PLL reference input to stabilize, in case the reference detection circuit validates the input too soon. The duration can range from 30 µs to 300 ms and programmed in R119[3-2]. Recommended duration for PLL as clock generator (loop bandwidth > 10 kHz) is 300 µs and for PLL as jitter cleaner (loop bandwidth < 1 kHz) is 300 ms. |
| TVCO | Step 4: VCO wait period | Programmable cycles of internal 10 MHz oscillator. | This counter is needed for the VCO to stabilize. The duration can range from 20 µs to 200 ms and programmed in R119[1-0]. Recommended duration for VCO1 is 400 µs. |
| TLOCK-PLL | Step 5: PLL lock time | ~4/LBW of PLL | The Outputs turn on immediately after calibration. A small frequency error remains for the duration of ~4/LBW (so in clock generator mode typically 10 µs for a PLL bandwidth of 400 kHz). The initial output frequency will be lower than the target output frequency, as the loop filter starts out initially discharged. |
| TLOL-PLL | Step 6: PLL LOL indicator low | ~1 PFD clock cycle | The PLL loss of lock indicator if selected on STATUS0 or STATUS1 will go low after 1 PFD clock cycle to indicate PLL is now locked. |
The LMK03318 start-up time for the PLL is defined as the time taken, from the moment the core supplies reach 2.72 V and VDDO_01 reaches 1.7 V, for the PLL to be locked and valid outputs are available at the outputs with no more than ±300 ppm error. Start-up time for the PLL can be calculated as Equation 5