JAJSFA5E September   2015  – April 2018 LMK03318

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      LMK03318概略ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 デバイス比較表
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Thermal Information
    6. 8.6  Electrical Characteristics - Power Supply
    7. 8.7  Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    8. 8.8  Non-Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    9. 8.9  Clock Input Characteristics (PRIREF_P/PRIREF_N, SECREF_P/SECREF_N)
    10. 8.10 VCO Characteristics
    11. 8.11 PLL Characteristics
    12. 8.12 1.8-V LVCMOS Output Characteristics (OUT[7:0])
    13. 8.13 LVCMOS Output Characteristics (STATUS[1:0])
    14. 8.14 Open-Drain Output Characteristics (STATUS[1:0])
    15. 8.15 AC-LVPECL Output Characteristics
    16. 8.16 AC-LVDS Output Characteristics
    17. 8.17 AC-CML Output Characteristics
    18. 8.18 HCSL Output Characteristics
    19. 8.19 Power-On Reset Characteristics
    20. 8.20 2-Level Logic Input Characteristics (HW_SW_CTRL, PDN, GPIO[5:0])
    21. 8.21 3-Level Logic Input Characteristics (REFSEL, GPIO[3:1])
    22. 8.22 Analog Input Characteristics (GPIO[5])
    23. 8.23 I2C-Compatible Interface Characteristics (SDA, SCL)
    24. 8.24 Typical 156.25-MHz Closed-Loop Output Phase Noise Characteristics
    25. 8.25 Typical 161.1328125-MHz Closed-Loop Output Phase Noise Characteristics
    26. 8.26 Closed-Loop Output Jitter Characteristics
    27. 8.27 PCIe Clock Output Jitter
    28. 8.28 Typical Power Supply Noise Rejection Characteristics
    29. 8.29 Typical Power-Supply Noise Rejection Characteristics
    30. 8.30 Typical Closed-Loop Output Spur Characteristics
    31. 8.31 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Test Configurations
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Device Block-Level Description
      2. 10.3.2 Device Configuration Control
        1. 10.3.2.1 Hard-Pin Mode (HW_SW_CTRL = 1)
          1. 10.3.2.1.1 PLL Block
          2. 10.3.2.1.2 Output Buffer Auto Mute
          3. 10.3.2.1.3 Input Block
          4. 10.3.2.1.4 Channel Mux
          5. 10.3.2.1.5 Output Divider
          6. 10.3.2.1.6 Output Driver Format
          7. 10.3.2.1.7 Status MUX, Divider and Slew Rate
        2. 10.3.2.2 Soft-Pin Programming Mode (HW_SW_CTRL = 0)
          1. 10.3.2.2.1 Device Config Space
          2. 10.3.2.2.2 PLL Block
          3. 10.3.2.2.3 Output Buffer Auto Mute
          4. 10.3.2.2.4 Input Block
          5. 10.3.2.2.5 Channel Mux
          6. 10.3.2.2.6 Output Divider
          7. 10.3.2.2.7 Output Driver Format
          8. 10.3.2.2.8 Status MUX, Divider and Slew Rate
        3. 10.3.2.3 Register File Reference Convention
    4. 10.4 Device Functional Modes
      1. 10.4.1  Smart Input MUX
      2. 10.4.2  Universal Input Buffer (PRI_REF, SEC_REF)
      3. 10.4.3  Crystal Input Interface (SEC_REF)
      4. 10.4.4  Reference Doubler
      5. 10.4.5  Reference Divider (R)
      6. 10.4.6  Input Divider (M)
      7. 10.4.7  Feedback Divider (N)
      8. 10.4.8  Phase Frequency Detector (PFD)
      9. 10.4.9  Charge Pump
      10. 10.4.10 Loop Filter
      11. 10.4.11 VCO Calibration
      12. 10.4.12 Fractional Circuitry
        1. 10.4.12.1 Programmable Dithering Levels
        2. 10.4.12.2 Programmable Delta Sigma Modulator Order
      13. 10.4.13 Post Divider
      14. 10.4.14 High-Speed Output MUX
      15. 10.4.15 High-Speed Output Divider
      16. 10.4.16 High-Speed Clock Outputs
      17. 10.4.17 Output Synchronization
      18. 10.4.18 Status Outputs
        1. 10.4.18.1 Loss of Reference
        2. 10.4.18.2 Loss of Lock
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Interface
      2. 10.5.2 Block Register Write
      3. 10.5.3 Block Register Read
      4. 10.5.4 Write SRAM
      5. 10.5.5 Write EEPROM
      6. 10.5.6 Read SRAM
      7. 10.5.7 Read EEPROM
      8. 10.5.8 Read ROM
      9. 10.5.9 Default Device Configurations in EEPROM and ROM
    6. 10.6 Register Maps
      1. 10.6.1   VNDRID_BY1 Register; R0
      2. 10.6.2   VNDRID_BY0 Register; R1
      3. 10.6.3   PRODID Register; R2
      4. 10.6.4   REVID Register; R3
      5. 10.6.5   PARTID Register; R4
      6. 10.6.6   PINMODE_SW Register; R8
      7. 10.6.7   PINMODE_HW Register; R9
      8. 10.6.8   SLAVEADR Register; R10
      9. 10.6.9   EEREV Register; R11
      10. 10.6.10  DEV_CTL Register; R12
      11. 10.6.11  INT_LIVE Register; R13
      12. 10.6.12  INT_MASK Register; R14
      13. 10.6.13  INT_FLAG_POL Register; R15
      14. 10.6.14  INT_FLAG Register; R16
      15. 10.6.15  INTCTL Register; R17
      16. 10.6.16  OSCCTL2 Register; R18
      17. 10.6.17  STATCTL Register; R19
      18. 10.6.18  MUTELVL1 Register; R20
      19. 10.6.19  MUTELVL2 Register; R21
      20. 10.6.20  OUT_MUTE Register; R22
      21. 10.6.21  STATUS_MUTE Register; R23
      22. 10.6.22  DYN_DLY Register; R24
      23. 10.6.23  REFDETCTL Register; R25
      24. 10.6.24  STAT0_INT Register; R27
      25. 10.6.25  STAT1 Register; R28
      26. 10.6.26  OSCCTL1 Register; R29
      27. 10.6.27  PWDN Register; R30
      28. 10.6.28  OUTCTL_0 Register; R31
      29. 10.6.29  OUTCTL_1 Register; R32
      30. 10.6.30  OUTDIV_0_1 Register; R33
      31. 10.6.31  OUTCTL_2 Register; R34
      32. 10.6.32  OUTCTL_3 Register; R35
      33. 10.6.33  OUTDIV_2_3 Register; R36
      34. 10.6.34  OUTCTL_4 Register; R37
      35. 10.6.35  OUTDIV_4 Register; R38
      36. 10.6.36  OUTCTL_5 Register; R39
      37. 10.6.37  OUTDIV_5 Register; R40
      38. 10.6.38  OUTCTL_6 Register; R41
      39. 10.6.39  OUTDIV_6 Register; R42
      40. 10.6.40  OUTCTL_7 Register; R43
      41. 10.6.41  OUTDIV_7 Register; R44
      42. 10.6.42  CMOSDIVCTRL Register; R45
      43. 10.6.43  CMOSDIV0 Register; R46
      44. 10.6.44  STATUS_SLEW Register; R49
      45. 10.6.45  IPCLKSEL Register; R50
      46. 10.6.46  IPCLKCTL Register; R51
      47. 10.6.47  PLL_RDIV Register; R52
      48. 10.6.48  PLL_MDIV Register; R53
      49. 10.6.49  PLL_CTRL0 Register; R56
      50. 10.6.50  PLL_CTRL1 Register; R57
      51. 10.6.51  PLL_NDIV_BY1 Register; R58
      52. 10.6.52  PLL_NDIV_BY0 Register; R59
      53. 10.6.53  PLL_FRACNUM_BY2 Register; R60
      54. 10.6.54  PLL_FRACNUM_BY1 Register; R61
      55. 10.6.55  PLL_FRACNUM_BY0 Register; R62
      56. 10.6.56  PLL_FRACDEN_BY2 Register; R63
      57. 10.6.57  PLL_FRACDEN_BY1 Register; R64
      58. 10.6.58  PLL_FRACDEN_BY0 Register; R65
      59. 10.6.59  PLL_MASHCTRL Register; R66
      60. 10.6.60  PLL_LF_R2 Register; R67
      61. 10.6.61  PLL_LF_C1 Register; R68
      62. 10.6.62  PLL_LF_R3 Register; R69
      63. 10.6.63  PLL_LF_C3 Register; R70
      64. 10.6.64  SEC_CTRL Register; R72
      65. 10.6.65  XO_MARGINING Register; R86
      66. 10.6.66  XO_OFFSET_GPIO5_STEP_1_BY1 Register; R88
      67. 10.6.67  XO_OFFSET_GPIO5_STEP_1_BY0 Register; R89
      68. 10.6.68  XO_OFFSET_GPIO5_STEP_2_BY1 Register; R90
      69. 10.6.69  XO_OFFSET_GPIO5_STEP_2_BY0 Register; R91
      70. 10.6.70  XO_OFFSET_GPIO5_STEP_3_BY1 Register; R92
      71. 10.6.71  XO_OFFSET_GPIO5_STEP_3_BY0 Register; R93
      72. 10.6.72  XO_OFFSET_GPIO5_STEP_4_BY1 Register; R94
      73. 10.6.73  XO_OFFSET_GPIO5_STEP_4_BY0 Register; R95
      74. 10.6.74  XO_OFFSET_GPIO5_STEP_5_BY1 Register; R96
      75. 10.6.75  XO_OFFSET_GPIO5_STEP_5_BY0 Register; R97
      76. 10.6.76  XO_OFFSET_GPIO5_STEP_6_BY1 Register; R98
      77. 10.6.77  XO_OFFSET_GPIO5_STEP_6_BY0 Register; R99
      78. 10.6.78  XO_OFFSET_GPIO5_STEP_7_BY1 Register; R100
      79. 10.6.79  XO_OFFSET_GPIO5_STEP_7_BY0 Register; R101
      80. 10.6.80  XO_OFFSET_GPIO5_STEP_8_BY1 Register; R102
      81. 10.6.81  XO_OFFSET_GPIO5_STEP_8_BY0 Register; R103
      82. 10.6.82  XO_OFFSET_SW_BY1 Register; R104
      83. 10.6.83  XO_OFFSET_SW_BY0 Register; R105
      84. 10.6.84  PLL_CTRL2 Register; R117
      85. 10.6.85  PLL_CTRL3 Register; R118
      86. 10.6.86  PLL_CALCTRL0 Register; R119
      87. 10.6.87  PLL_CALCTRL1 Register; R120
      88. 10.6.88  NVMCNT Register; R136
      89. 10.6.89  NVMCTL Register; R137
      90. 10.6.90  NVMLCRC Register; R138
      91. 10.6.91  MEMADR_BY1 Register; R139
      92. 10.6.92  MEMADR_BY0 Register; R140
      93. 10.6.93  NVMDAT Register; R141
      94. 10.6.94  RAMDAT Register; R142
      95. 10.6.95  ROMDAT Register; R143
      96. 10.6.96  NVMUNLK Register; R144
      97. 10.6.97  REGCOMMIT_PAGE Register; R145
      98. 10.6.98  XOCAPCTRL_BY1 Register; R199
      99. 10.6.99  XOCAPCTRL_BY0 Register; R200
      100. 10.6.100 EEPROM Map
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Application Block Diagram Examples
      2. 11.2.2 Jitter Considerations in Serdes Systems
      3. 11.2.3 Frequency Margining
        1. 11.2.3.1 Fine Frequency Margining
        2. 11.2.3.2 Coarse Frequency Margining
      4. 11.2.4 Design Requirements
        1. 11.2.4.1 Detailed Design Procedure
          1. 11.2.4.1.1 Device Selection
            1. 11.2.4.1.1.1 Calculation Using LCM
          2. 11.2.4.1.2 Device Configuration
          3. 11.2.4.1.3 PLL Loop Filter Design
            1. 11.2.4.1.3.1 PLL Loop Filter Design
          4. 11.2.4.1.4 Clock Output Assignment
        2. 11.2.4.2 Spur Mitigation Techniques
          1. 11.2.4.2.1 Phase Detector Spurs
          2. 11.2.4.2.2 Integer Boundary Fractional Spurs
          3. 11.2.4.2.3 Primary Fractional Spurs
          4. 11.2.4.2.4 Sub-Fractional Spurs
  12. 12Power Supply Recommendations
    1. 12.1 Device Power Up Sequence
    2. 12.2 Device Power Up Timing
    3. 12.3 Power Down
    4. 12.4 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
      1. 12.4.1 Mixing Supplies
      2. 12.4.2 Power-On Reset
      3. 12.4.3 Powering Up From Single-Supply Rail
      4. 12.4.4 Powering Up From Split-Supply Rails
      5. 12.4.5 Slow Power-Up Supply Ramp
      6. 12.4.6 Non-Monotonic Power-Up Supply Ramp
      7. 12.4.7 Slow Reference Input Clock Startup
    5. 12.5 Power Supply Bypassing
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Ensure Thermal Reliability
      2. 13.1.2 Support for PCB Temperature up to 105°C
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.5.9 Default Device Configurations in EEPROM and ROM

Table 10 through Table 13 show the device default configurations stored in the on-chip EEPROM. Table 14 through Table 18 show the device default configurations stored in the on-chip ROM.

Table 10. Default EEPROM Contents (HW_SW_CTRL = 0) – Input and Status Configuration(1)(2)

GPIO [3:2] PRI INPUT (MHz) PRI TYPE PRI DOUBLER SEC INPUT (MHz) SEC TYPE XO INT LOAD (pF) SEC DOUBLER STATUS1 MUX STATUS0 MUX PREDIV DIV STATUS1 / STATUS0 FREQ (MHz) STATUS1 / STATUS0 RISE / FALL TIME (ns)
VIM, VIM 25 DIFF Enabled 25 XTAL 9 Enabled LOL Disable n/a n/a n/a n/a
00 25 DIFF Enabled 25 XTAL 9 Enabled LOL PLL 4 25 n/a / 50 n/a / 2.1
01 25 LVCMOS Enabled 25 XTAL 9 Enabled LOL PLL 4 25 n/a / 50 n/a / 2.1
(1) 100-Ω internal termination enabled (if applicable)
(2) Internal AC biasing enabled (if applicable)

Table 11. Default EEPROM Contents (HW_SW_CTRL = 0) – PLL Configuration(1)

GPIO [3:2] PLL INPUT MUX PLL INPUT (MHz) PLL TYPE PLL R DIV PLL M DIV PLL N DIV PLL N DIV INT PLL N DIV NUM PLL N DIV DEN PLL FRAC ORDER PLL FRAC DITHER PLL VCO (MHz) PLL P DIV
VIM, VIM REFSEL 50 Clock Gen Integer 1 1 102 102 0 1 n/a Disabled 5100 8
00 REFSEL 50 Clock Gen Integer 1 1 100 100 0 4000000 n/a Disabled 5000 2
01 REFSEL 50 Clock Gen Integer 1 1 100 100 0 4000000 n/a Disabled 5000 2
(1) When PLL is set as an integer-based clock generator, external loop filter component, C2, should be 3.3 nF and loop bandwidth is around 400 kHz. When PLL is set as a fractional-based clock generator, external loop filter component, C2, should be 33 nF and loop bandwidth is around 400 kHz.

Table 12. Default EEPROM Contents (HW_SW_CTRL = 0) – Outputs [0-3] Configuration

GPIO [3:2] OUT0-1 DIVIDER OUT0-1 FREQ (MHz) OUT0 TYPE OUT1 TYPE OUT2-3 DIVIDER OUT2-3 FREQ (MHz) OUT2 TYPE OUT3 TYPE
VIM, VIM n/a n/a Disable Disable n/a n/a Disable Disable
00 25 100 LVPECL LVCMOS (+/-) 25 100 LVCMOS (+/-) LVCMOS (+/-)
01 25 100 LVCMOS (+/-) LVCMOS (+/-) 25 100 LVCMOS (+/-) LVCMOS (+/-)

Table 13. Default EEPROM Contents (HW_SW_CTRL = 0) – Outputs [4-7] Configuration

GPIO [3:2] OUT4 DIV OUT4 FREQ (MHz) OUT4 MUX SELECT OUT4 TYPE OUT5 DIV OUT5 FREQ (MHz) OUT5 MUX SELECT OUT5 TYPE OUT6 DIV OUT6 FREQ (MHz) OUT6 MUX SELECT OUT6 TYPE OUT7 DIV OUT7 FREQ (MHz) OUT7 MUX SELECT OUT7 TYPE
VIM, VIM 3 212.5 PLL LVPECL 3 212.5 PLL LVPECL 6 106.25 PLL LVPECL 6 106.25 PLL LVPECL
00 16 156.25 PLL LVPECL 20 125 PLL LVPECL 20 125 PLL LVDS 100 25 PLL LVPECL
01 25 100 PLL LVCMOS (+/-) 20 125 PLL LVDS 20 125 PLL LVDS 20 125 PLL LVDS

Table 14. Default ROM Contents (HW_SW_CTRL = 1) - Input Configuration

GPIO[5:0] (decimal) PRI INPUT (MHz) PRI TYPE PRI DOUBLER SEC INPUT (MHz) SEC TYPE XO INT LOAD (pF) SEC DOUBLER
0 50 LVCMOS Enabled 50 XTAL 9 Enabled
1 50 LVCMOS Enabled 50 XTAL 9 Enabled
2 50 LVCMOS Enabled 50 XTAL 9 Enabled
3 50 LVCMOS Enabled 50 XTAL 9 Enabled
4 50 LVCMOS Enabled 50 XTAL 9 Enabled
5 50 LVCMOS Enabled 50 XTAL 9 Enabled
6 30.72 LVCMOS Disabled 30.72 XTAL 9 Disabled
7 19.2 LVCMOS Disabled 19.2 XTAL 9 Disabled
8 10 LVCMOS Disabled 10 XTAL 9 Disabled
9 25 LVCMOS Enabled 25 XTAL 9 Enabled
10 50 LVCMOS Enabled 50 XTAL 9 Enabled
11 25 LVCMOS Enabled 25 XTAL 9 Enabled
12 50 LVCMOS Enabled 50 XTAL 9 Enabled
13 25 LVCMOS Enabled 25 XTAL 9 Enabled
14 50 LVCMOS Enabled 50 XTAL 9 Enabled
15 25 LVCMOS Enabled 25 XTAL 9 Enabled
16 50 LVCMOS Enabled 50 XTAL 9 Enabled
17 25 LVCMOS Enabled 25 XTAL 9 Enabled
18 50 LVCMOS Enabled 50 XTAL 9 Enabled
19 25 LVCMOS Enabled 25 XTAL 9 Enabled
20 50 LVCMOS Enabled 50 XTAL 9 Enabled
21 19.44 LVCMOS Disabled 19.44 XTAL 9 Disabled
22 38.88 LVCMOS Disabled 38.88 XTAL 9 Disabled
23 25 LVCMOS Enabled 25 XTAL 9 Enabled
24 50 LVCMOS Enabled 50 XTAL 9 Enabled
25 19.44 LVCMOS Disabled 19.44 XTAL 9 Disabled
26 38.88 LVCMOS Disabled 38.88 XTAL 9 Disabled
27 25 LVCMOS Enabled 25 XTAL n/a Enabled
28 25 LVCMOS Enabled 25 XTAL n/a Enabled
29 25 LVCMOS Enabled 25 XTAL 9 Enabled
30 50 LVCMOS Enabled 50 XTAL 9 Enabled
31 25 LVCMOS Enabled 25 XTAL n/a Enabled
32 25 LVCMOS Enabled 25 LVCMOS n/a Enabled
33 25 LVCMOS Enabled 25 XTAL 9 Enabled
34 50 LVCMOS Enabled 50 XTAL 9 Enabled
35 19.44 LVCMOS Disabled 19.44 XTAL 9 Disabled
36 38.88 LVCMOS Disabled 38.88 XTAL 9 Disabled
37 25 LVCMOS Enabled 25 XTAL 9 Enabled
38 50 LVCMOS Enabled 50 XTAL 9 Enabled
39 19.44 LVCMOS Disabled 19.44 XTAL 9 Disabled
40 38.88 LVCMOS Disabled 38.88 XTAL 9 Disabled
41 19.44 LVCMOS Disabled 19.44 XTAL 9 Disabled
42 38.88 LVCMOS Disabled 38.88 XTAL 9 Disabled
43 19.44 LVCMOS Disabled 19.44 XTAL 9 Disabled
44 38.88 LVCMOS Disabled 38.88 XTAL 9 Disabled
45 25 LVCMOS Enabled 25 XTAL 9 Enabled
46 50 LVCMOS Enabled 50 XTAL 9 Enabled
47 25 LVCMOS Enabled 25 XTAL 9 Enabled
48 50 LVCMOS Enabled 50 XTAL 9 Enabled
49 25 LVCMOS Enabled 25 XTAL 9 Enabled
50 50 LVCMOS Enabled 50 XTAL 9 Enabled
51 25 LVCMOS Enabled 25 XTAL 9 Enabled
52 50 LVCMOS Enabled 50 XTAL 9 Enabled
53 25 LVCMOS Enabled 25 XTAL 9 Enabled
54 50 LVCMOS Enabled 50 XTAL 9 Enabled
55 19.44 LVCMOS Disabled 19.44 XTAL 9 Disabled
56 38.88 LVCMOS Disabled 38.88 XTAL 9 Disabled
57 25 LVCMOS Enabled 25 XTAL 9 Enabled
58 25 LVCMOS Enabled 25 XTAL 9 Enabled
59 25 LVCMOS Enabled 25 XTAL 9 Enabled
60 50 LVCMOS Enabled 50 XTAL 9 Enabled
61 25 LVCMOS Enabled 25 XTAL 9 Enabled
62 50 LVCMOS Enabled 50 XTAL 9 Enabled
63 25 LVCMOS Enabled 25 XTAL 9 Enabled

Table 15. Default ROM Contents (HW_SW_CTRL = 1) - Status Configuration

GPIO[5:0] (decimal) STATUS1 MUX STATUS0 MUX STATUS1 PREDIV STATUS1 DIV STATUS1 FREQ (MHz) STATUS1 RISE/FALL TIME (ns) STATUS0 PREDIV STATUS0 DIV STATUS0 FREQ (MHz) STATUS0 RISE/FALL TIME (ns)
0 LOL PLL n/a n/a n/a n/a 5 20 50 2.1
1 LOL PLL n/a n/a n/a n/a 5 40 25 2.1
2 LOL LOR_PRI n/a n/a n/a n/a n/a n/a n/a n/a
3 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
4 LOL LOR_PRI n/a n/a n/a n/a n/a n/a n/a n/a
5 PLL PLL 5 40 25 2.1 5 40 25 2.1
6 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
7 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
8 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
9 PLL LOL 4 51 25 2.1 n/a n/a n/a n/a
10 PLL LOL 4 51 25 2.1 n/a n/a n/a n/a
11 PLL LOL 5 30 33.3333 2.1 n/a n/a n/a n/a
12 PLL LOL 5 30 33.3333 2.1 n/a n/a n/a n/a
13 PLL LOL 4 51 25 2.1 n/a n/a n/a n/a
14 PLL LOL 4 51 25 2.1 n/a n/a n/a n/a
15 PLL LOL 4 51 25 2.1 n/a n/a n/a n/a
16 PLL LOL 4 51 25 2.1 n/a n/a n/a n/a
17 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
18 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
19 PLL LOL 5 40 25 2.1 n/a n/a n/a n/a
20 PLL LOL 5 40 25 2.1 n/a n/a n/a n/a
21 PLL LOL 5 40 25 2.1 n/a n/a n/a n/a
22 PLL LOL 5 40 25 2.1 n/a n/a n/a n/a
23 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
24 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
25 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
26 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
27 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
28 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
29 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
30 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
31 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
32 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
33 PLL LOL 5 15 66.6666 2.1 n/a n/a n/a n/a
34 PLL LOL 5 15 66.6666 2.1 n/a n/a n/a n/a
35 PLL LOL 5 15 66.6666 2.1 n/a n/a n/a n/a
36 PLL LOL 5 15 66.6666 2.1 n/a n/a n/a n/a
37 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
38 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
39 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
40 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
41 PLL LOL 4 32 38.88 2.1 n/a n/a n/a n/a
42 PLL LOL 4 32 38.88 2.1 n/a n/a n/a n/a
43 PLL LOL 4 32 38.88 2.1 n/a n/a n/a n/a
44 PLL LOL 4 32 38.88 2.1 n/a n/a n/a n/a
45 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
46 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
47 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
48 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
49 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
50 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
51 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
52 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
53 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
54 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
55 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
56 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
57 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
58 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
59 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
60 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
61 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
62 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a
63 LOR_PRI LOL n/a n/a n/a n/a n/a n/a n/a n/a

Table 16. Default ROM Contents (HW_SW_CTRL = 1) – PLL Configuration(1)

GPIO[5:0] (decimal) PLL IN MUX PLL IN (MHz) PLL TYPE PLL R DIV PLL M DIV PLL N DIV PLL N DIV INT PLL N DIV NUM PLL N DIV DEN PLL FRAC ORDER PLL FRAC DITHER PLL VCO (MHz) PLL P DIV
0 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 5
1 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 5
2 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 5
3 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 4
4 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 2
5 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 2
6 REFSEL 30.72 Jitter Cleaner Integer 1 24 3840 3840 0 1 n/a Disabled 4915.2 4
7 REFSEL 19.2 Clock Gen Integer 1 1 256 256 0 1 n/a Disabled 4915.2 4
8 REFSEL 10 Clock Gen Integer 1 1 491.52 491 1300000 2500000 Third Enabled 4915.2 4
9 REFSEL 25 Clock Gen Fractional 1 1 102 102 0 1 n/a Disabled 5100 8
10 REFSEL 50 Clock Gen Integer 1 1 51 51 0 1 n/a Disabled 5100 8
11 REFSEL 25 Clock Gen Fractional 1 1 100 100 0 1 n/a Disabled 5000 2
12 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 2
13 REFSEL 25 Clock Gen Integer 1 1 102 102 0 1 n/a Disabled 5100 3
14 REFSEL 50 Clock Gen Integer 1 1 51 51 0 1 n/a Disabled 5100 3
15 REFSEL 25 Clock Gen Integer 1 1 102 102 0 1 n/a Disabled 5100 3
16 REFSEL 50 Clock Gen Integer 1 1 51 51 0 1 n/a Disabled 5100 3
17 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
18 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 8
19 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
20 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 8
21 REFSEL 19.44 Clock Gen Integer 1 1 257.2016461 257 157536 781250 Third Enabled 5000 8
22 REFSEL 38.88 Clock Gen Integer 1 1 128.600823 128 469393 781250 Third Enabled 5000 8
23 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 2
24 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 2
25 REFSEL 19.44 Clock Gen Integer 1 1 257.2016461 257 157536 781250 Third Enabled 5000 2
26 REFSEL 38.88 Clock Gen Integer 1 1 128.600823 128 469393 781250 Third Enabled 5000 2
27 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 2
28 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
29 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
30 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 2
31 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 2
32 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 2
33 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
34 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 8
35 REFSEL 19.44 Clock Gen Integer 1 1 257.2016461 257 157536 781250 Third Enabled 5000 8
36 REFSEL 38.88 Clock Gen Fractional 1 1 128.600823 128 469393 781250 Third Enabled 5000 8
37 REFSEL 25 Clock Gen Fractional 1 1 100 100 0 1 n/a Disabled 5000 8
38 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 8
39 REFSEL 19.44 Clock Gen Integer 1 1 257.2016461 257 157536 781250 Third Enabled 5000 8
40 REFSEL 38.88 Clock Gen Fractional 1 1 128.600823 128 469393 781250 Third Enabled 5000 8
41 REFSEL 19.44 Clock Gen Integer 1 1 256 256 0 1 n/a Disabled 4976.64 8
42 REFSEL 38.88 Clock Gen Fractional 1 1 128 128 0 1 n/a Disabled 4976.64 8
43 REFSEL 19.44 Clock Gen Integer 1 1 256 256 0 1 n/a Disabled 4976.64 8
44 REFSEL 38.88 Clock Gen Fractional 1 1 128 128 0 1 n/a Disabled 4976.64 8
45 REFSEL 25 Clock Gen Fractional 1 1 100 100 0 1 n/a Disabled 5000 5
46 REFSEL 50 Clock Gen Fractional 1 1 50 50 0 1 n/a Disabled 5000 5
47 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
48 REFSEL 50 Clock Gen Fractional 1 1 50 50 0 1 n/a Disabled 5000 8
49 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
50 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 8
51 REFSEL 25 Clock Gen Fractional 1 1 106.25 106 1000000 4000000 First Enabled 5312.5 2
52 REFSEL 50 Clock Gen Fractional 1 1 53.125 53 500000 4000000 First Enabled 5312.5 2
53 REFSEL 25 Clock Gen Integer 1 1 103.125 103 500000 4000000 First Enabled 5156.25 8
54 REFSEL 50 Clock Gen Fractional 1 1 51.5625 51 2250000 4000000 First Enabled 5156.25 8
55 REFSEL 19.44 Clock Gen Fractional 1 1 265.2391976 265 597994 2500000 Third Enabled 5156.25 8
56 REFSEL 38.88 Clock Gen Integer 1 1 132.6195988 132 1548997 2500000 Third Enabled 5156.25 8
57 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 2
58 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 2
59 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
60 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 8
61 REFSEL 25 Clock Gen Integer 1 1 100 100 0 1 n/a Disabled 5000 8
62 REFSEL 50 Clock Gen Integer 1 1 50 50 0 1 n/a Disabled 5000 8
63 REFSEL 25 Clock Gen Fractional 1 1 100 100 0 1 n/a Disabled 5000 8
(1) When PLL is set as an integer-based clock generator, external loop filter component, C2, should be 3.3nF and loop bandwidth is around 400kHz. When PLL is set as a fractional-based clock generator, external loop filter component, C2, should be 33nF and loop bandwidth is around 400kHz.

Table 17. Default ROM Contents (HW_SW_CTRL = 1) - Outputs [0-4] Configuration

GPIO[5:0] (decimal) OUT0-1 DIVIDER OUT0-1 FREQ (MHz) OUT0 TYPE OUT1 TYPE OUT2-3 DIVIDER OUT2-3 FREQ (MHz) OUT2 TYPE OUT3 TYPE OUT4 DIV OUT4 FREQ (MHz) OUT4 MUX SELECT OUT4 TYPE
0 5 200 LVDS LVDS 10 100 LVDS LVDS 1 n/a n/a Disable
1 5 200 LVDS LVDS 10 100 LVDS LVDS 1 n/a n/a Disable
2 10 100 LVDS LVDS 10 100 LVDS LVDS 8 125 PLL LVDS
3 4 312.5 LVDS LVDS 8 156.25 LVPECL LVPECL 10 125 PLL LVDS
4 20 125 LVPECL LVPECL 16 156.25 LVPECL LVPECL 25 100 PLL LVPECL
5 16 156.25 LVPECL LVPECL 16 156.25 LVPECL LVPECL 16 156.25 PLL LVPECL
6 4 307.2 LVPECL LVPECL 5 245.76 LVDS LVDS 8 153.6 PLL LVDS
7 4 307.2 LVPECL LVPECL 5 245.76 LVPECL LVPECL 8 153.6 PLL LVDS
8 4 307.2 LVPECL LVPECL 5 245.76 LVDS LVDS 8 153.6 PLL LVDS
9 6 106.25 LVPECL LVPECL 6 106.25 LVPECL LVPECL 3 212.5 PLL LVPECL
10 6 106.25 LVDS LVDS 6 106.25 LVDS LVDS 3 212.5 PLL LVDS
11 16 156.25 LVPECL LVPECL 20 125 LVPECL LVPECL 25 100 PLL HCSL
12 16 156.25 LVDS LVDS 20 125 LVDS LVDS 25 100 PLL HCSL
13 16 106.25 LVPECL LVPECL 16 106.25 LVPECL LVPECL 17 100 PLL HCSL
14 16 106.25 LVDS LVDS 16 106.25 LVDS LVDS 17 100 PLL HCSL
15 4 425 LVPECL LVPECL 8 212.5 LVPECL LVPECL 17 100 PLL HCSL
16 4 425 LVDS LVDS 8 212.5 LVDS LVDS 17 100 PLL HCSL
17 4 156.25 LVPECL LVPECL 4 156.25 LVPECL LVPECL 4 156.25 PLL LVPECL
18 4 156.25 LVDS LVDS 4 156.25 LVDS LVDS 4 156.25 PLL LVDS
19 4 156.25 LVPECL LVPECL 4 156.25 LVPECL LVPECL 4 156.25 PLL LVPECL
20 4 156.25 LVDS LVDS 4 156.25 LVDS LVDS 4 156.25 PLL LVDS
21 4 156.25 LVPECL LVPECL 4 156.25 LVPECL LVPECL 4 156.25 PLL LVPECL
22 4 156.25 LVDS LVDS 4 156.25 LVDS LVDS 4 156.25 PLL LVDS
23 16 156.25 LVPECL LVPECL 16 156.25 LVPECL LVPECL 25 100 PLL LVDS
24 16 156.25 LVDS LVDS 16 156.25 LVDS LVDS 25 100 PLL LVDS
25 16 156.25 LVPECL LVPECL 16 156.25 LVPECL LVPECL 25 100 PLL LVDS
26 16 156.25 LVDS LVDS 16 156.25 LVDS LVDS 25 100 PLL LVDS
27 16 156.25 LVPECL LVPECL 25 100 LVPECL LVPECL 50 50 PLL LVPECL
28 4 156.25 LVPECL LVPECL 4 156.25 LVPECL LVPECL 4 156.25 PLL LVPECL
29 4 156.25 LVPECL LVPECL 4 156.25 LVPECL LVPECL 4 156.25 PLL LVPECL
30 8 312.5 LVDS LVDS 16 156.25 LVPECL LVPECL 16 156.25 PLL LVDS
31 16 156.25 LVPECL LVPECL 16 156.25 LVPECL LVPECL 16 156.25 PLL LVPECL
32 4 625 LVDS LVDS 4 625 LVPECL LVPECL 25 100 PLL LVDS
33 4 156.25 LVPECL LVPECL 4 156.25 LVPECL LVPECL 4 156.25 PLL LVPECL
34 4 156.25 LVDS LVDS 4 156.25 LVPECL LVPECL 4 156.25 PLL LVDS
35 4 156.25 LVPECL LVPECL 4 156.25 LVPECL LVPECL 4 156.25 PLL LVPECL
36 4 156.25 LVDS LVDS 4 156.25 LVPECL LVPECL 4 156.25 PLL LVDS
37 4 156.25 LVPECL LVPECL 5 125 LVDS LVDS 5 125 PLL LVDS
38 4 156.25 LVDS LVDS 5 125 LVDS LVDS 5 125 PLL LVDS
39 4 156.25 LVPECL LVPECL 5 125 HCSL HCSL 5 125 PLL LVDS
40 4 156.25 LVDS LVDS 5 125 LVDS LVDS 5 125 PLL LVDS
41 2 311.04 LVPECL LVPECL 4 155.52 LVDS LVDS 4 155.52 PLL LVPECL
42 2 311.04 LVDS LVDS 4 155.52 LVPECL LVPECL 4 155.52 PLL LVDS
43 1 622.08 LVPECL LVPECL 1 622.08 LVPECL LVPECL 4 155.52 PLL LVDS
44 1 622.08 LVDS LVDS 1 622.08 LVPECL LVPECL 4 155.52 PLL LVDS
45 10 100 LVPECL LVPECL 10 100 LVPECL LVPECL 4 250 PLL LVPECL
46 10 100 LVDS LVDS 10 100 LVPECL LVPECL 4 250 PLL LVDS
47 25 25 LVPECL LVPECL 2 312.5 LVPECL LVPECL 4 156.25 PLL LVPECL
48 25 25 LVDS LVDS 2 312.5 LVDS LVDS 4 156.25 PLL LVDS
49 25 25 LVPECL LVPECL 4 156.25 LVPECL LVPECL 4 156.25 PLL LVPECL
50 25 25 LVDS LVDS 4 156.25 LVDS LVDS 4 156.25 PLL LVDS
51 25 106.25 LVPECL LVPECL 25 106.25 LVPECL LVPECL 17 156.25 PLL LVPECL
52 25 106.25 LVDS LVDS 25 106.25 LVDS LVDS 17 156.25 PLL LVDS
53 4 161.1328125 LVPECL LVPECL 4 161.1328125 LVPECL LVPECL 2 322.265625 PLL LVPECL
54 4 161.1328125 LVDS LVDS 4 161.1328125 LVPECL LVPECL 2 322.265625 PLL LVDS
55 4 161.1328125 LVPECL LVPECL 4 161.1328125 LVPECL LVPECL 2 322.265625 PLL LVPECL
56 4 161.1328125 LVDS LVDS 4 161.1328125 LVPECL LVPECL 2 322.265625 PLL LVDS
57 16 156.25 LVPECL LVPECL 16 156.25 LVPECL LVPECL 25 100 PLL HCSL
58 16 156.25 LVDS LVDS 16 156.25 LVDS LVDS 25 100 PLL HCSL
59 2 312.5 LVPECL LVPECL 2 312.5 LVPECL LVPECL 2 312.5 PLL LVPECL
60 2 312.5 LVPECL LVPECL 2 312.5 LVPECL LVPECL 2 312.5 PLL LVPECL
61 4 156.25 LVPECL LVPECL 4 156.25 LVPECL LVPECL 4 156.25 PLL LVPECL
62 4 156.25 LVPECL LVPECL 4 156.25 LVPECL LVPECL 4 156.25 PLL LVPECL
63 5 125 LVPECL LVPECL 5 125 LVPECL LVPECL 5 125 PLL LVPECL

Table 18. Default ROM Contents (HW_SW_CTRL = 1) - Outputs [5-7] Configuration

GPIO[5:0] (decimal) OUT5 DIV OUT5 FREQ (MHz) OUT5 MUX SELECT OUT5 TYPE OUT6 DIV OUT6 FREQ (MHz) OUT6 MUX SELECT OUT6 TYPE OUT7 DIV OUT7 FREQ (MHz) OUT7 MUX SELECT OUT7 TYPE
0 1 n/a n/a Disable 1 n/a n/a Disable 1 n/a n/a Disable
1 1 n/a n/a Disable 1 n/a n/a Disable 1 n/a n/a Disable
2 8 125 PLL LVDS 8 125 PLL LVDS 8 125 PLL LVDS
3 10 125 PLL LVDS 25 50 PLL LVDS 25 50 PLL LVDS
4 20 125 PLL LVPECL 16 156.25 PLL LVPECL 16 156.25 PLL LVPECL
5 20 125 PLL LVPECL 20 125 PLL LVPECL 20 125 PLL LVPECL
6 8 153.6 PLL LVDS 10 122.88 PLL LVDS 10 122.88 PLL LVDS
7 8 153.6 PLL LVDS 10 122.88 PLL LVDS 10 122.88 PLL LVDS
8 8 153.6 PLL LVDS 10 122.88 PLL LVDS 10 122.88 PLL LVDS
9 3 212.5 PLL LVPECL 3 212.5 PLL LVPECL 3 212.5 PLL LVPECL
10 3 212.5 PLL LVDS 3 212.5 PLL LVDS 3 212.5 PLL LVDS
11 25 100 PLL HCSL 100 25 PLL LVDS 100 25 PLL LVCMOS
12 25 100 PLL HCSL 100 25 PLL LVDS 100 25 PLL LVCMOS
13 17 100 PLL HCSL 17 100 PLL HCSL 17 100 PLL HCSL
14 17 100 PLL HCSL 17 100 PLL HCSL 17 100 PLL HCSL
15 34 50 PLL LVDS 3 566.67 PLL LVPECL 16 106.25 PLL LVDS
16 34 50 PLL LVDS 3 566.67 PLL LVPECL 16 106.25 PLL LVDS
17 4 156.25 PLL LVPECL 5 125 PLL LVPECL 5 125 PLL LVPECL
18 4 156.25 PLL LVDS 5 125 PLL LVDS 5 125 PLL LVDS
19 5 125 PLL LVPECL 5 125 PLL LVPECL 5 125 PLL LVPECL
20 5 125 PLL LVDS 5 125 PLL LVDS 5 125 PLL LVDS
21 5 125 PLL LVPECL 5 125 PLL LVPECL 5 125 PLL LVPECL
22 5 125 PLL LVDS 5 125 PLL LVDS 5 125 PLL LVDS
23 25 100 PLL LVDS 20 125 PLL LVDS 20 125 PLL LVDS
24 25 100 PLL LVDS 20 125 PLL LVDS 20 125 PLL LVDS
25 25 100 PLL LVDS 20 125 PLL LVDS 20 125 PLL LVDS
26 25 100 PLL LVDS 20 125 PLL LVDS 20 125 PLL LVDS
27 20 125 PLL LVPECL 25 100 PLL LVCMOS 100 25 PLL LVCMOS
28 4 156.25 PLL LVPECL 4 156.25 PLL LVPECL 25 25 PLL LVCMOS
29 25 25 PLL LVCMOS 25 25 PLL LVCMOS 25 25 PLL LVCMOS
30 8 312.5 PLL LVDS 25 100 PLL LVDS 20 125 PLL LVDS
31 25 100 PLL HCSL 25 100 PLL HCSL 100 25 PLL LVPECL
32 25 100 PLL LVDS 25 100 PLL LVDS 25 100 PLL LVDS
33 4 156.25 PLL LVPECL 5 125 PLL LVDS 5 125 PLL LVCMOS
34 4 156.25 PLL LVDS 5 125 PLL LVDS 5 125 PLL LVCMOS
35 4 156.25 PLL LVPECL 5 125 PLL LVDS 5 125 PLL LVCMOS
36 4 156.25 PLL LVDS 5 125 PLL LVDS 5 125 PLL LVCMOS
37 4 156.25 PLL LVPECL 5 125 PLL LVDS 5 125 PLL LVCMOS
38 4 156.25 PLL LVDS 5 125 PLL LVDS 5 125 PLL LVCMOS
39 4 156.25 PLL LVPECL 5 125 PLL LVDS 5 125 PLL LVCMOS
40 4 156.25 PLL LVDS 5 125 PLL LVDS 5 125 PLL LVCMOS
41 4 155.52 PLL LVPECL 8 77.76 PLL LVDS 8 77.76 PLL LVDS
42 4 155.52 PLL LVDS 8 77.76 PLL LVDS 8 77.76 PLL LVDS
43 4 155.52 PLL LVDS 8 77.76 PLL LVDS 8 77.76 PLL LVDS
44 4 155.52 PLL LVDS 8 77.76 PLL LVDS 8 77.76 PLL LVDS
45 4 250 PLL LVPECL 40 25 PLL LVCMOS 15 66.67 PLL LVCMOS
46 4 250 PLL LVDS 40 25 PLL LVCMOS 15 66.67 PLL LVCMOS
47 10 62.5 PLL LVPECL 5 125 PLL LVPECL 2 312.5 PLL LVPECL
48 10 62.5 PLL LVDS 5 125 PLL LVDS 2 312.5 PLL LVDS
49 5 125 PLL LVPECL 5 125 PLL LVPECL 5 125 PLL LVPECL
50 5 125 PLL LVDS 5 125 PLL LVDS 5 125 PLL LVDS
51 17 156.25 PLL LVPECL 17 156.25 PLL LVPECL 17 156.25 PLL LVPECL
52 17 156.25 PLL LVDS 17 156.25 PLL LVDS 17 156.25 PLL LVDS
53 2 322.265625 PLL LVPECL 2 322.265625 PLL LVPECL 2 322.265625 PLL LVPECL
54 2 322.265625 PLL LVDS 2 322.265625 PLL LVDS 2 322.265625 PLL LVDS
55 2 322.265625 PLL LVPECL 2 322.265625 PLL LVPECL 2 322.265625 PLL LVPECL
56 2 322.265625 PLL LVDS 2 322.265625 PLL LVDS 2 322.265625 PLL LVDS
57 25 100 PLL HCSL 25 100 PLL HCSL 25 100 PLL HCSL
58 25 100 PLL HCSL 25 100 PLL HCSL 25 100 PLL HCSL
59 2 312.5 PLL LVPECL 2 312.5 PLL LVPECL 2 312.5 PLL LVPECL
60 2 312.5 PLL LVPECL 2 312.5 PLL LVPECL 2 312.5 PLL LVPECL
61 4 156.25 PLL LVPECL 4 156.25 PLL LVPECL 4 156.25 PLL LVPECL
62 4 156.25 PLL LVPECL 4 156.25 PLL LVPECL 4 156.25 PLL LVPECL
63 5 125 PLL LVPECL 5 125 PLL LVPECL 5 125 PLL LVPECL