JAJSFA4D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
In this mode, I2C is enabled and GPIO[3:2] are purposed as 3-state pins (tied to VDD_DIG, GND or VIM) and are used to select one of 6 EEPROM pages and one register default setting (2 of 9 states are invalid). GPIO[0] is also purposed as a 2-state output synchronization (active-low SYNCN) function, GPIO[1] is now purposed as a 3-state I2C address function to change last 2 bits of I2C address (ADD; 0x0 is GND, 0x1 is VIM, and 0x3 is VDD_DIG). GPIO[5] is purposed as a multi-state input for the MARGIN function and GPIO[4] is purposed as an input that enables or disables hardware margining. The GPIO pins are sampled and latched at POR.
NOTE
No software reset or power cycling should occur during EEPROM programming or else it will be corrupted. Refer to Programming for more details on the EEPROM programming.
GPIO[3:2] allows hardware pin configuration for the PLL synthesizers, their respective input clock selection modes, the crystal input frequency margining option, all output channel blocks, comprised of channel muxes, dividers, and output drivers. The GPIO inputs[3:2] are sampled and latched at power-on reset (POR), and select one of 6 EEPROM pages which are custom-programmable. When GPIO[3:2] are left floating, EEPROM is not used and the hardware register default settings are loaded. Table 10, Table 11, Table 12, Table 13, and Table 14 show the predefined EEPROM configurations according to the GPIO[3:2] pin settings.
Below is a brief overview of each block’s register settings configured by the GPIO[3:2] pin modes.