JAJSFA4D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
Each PLL has a dedicated Smart Input MUX. The input selection mode per PLL can be configured using the 3-state REFSEL pin or programmed through I2C. The Smart Input MUX supports auto switching and manual switching using control pin (or through register). The Smart Input MUX is designed such that glitches created during switching in both auto and manual modes are suppressed at the MUX output.
In the automatic mode, the frequencies of both primary (PRIREF) and secondary (SECREF) input clocks have to be within 2000 ppm. The phase of the input clocks can be any. To minimize phase jump at the output, TI recommends set very low PLL loop bandwidth, set R29.7 = 1, and R51.7 = 1; the outputs that are not muted should have its respective mute bypass bit in R20 and R21 be set to 0x0 to ensure that these outputs are available during an input switchover event. In the case that the primary reference is detected to be unavailable, the input MUX automatically switches from the primary reference to the secondary reference. When primary reference is detected to be available again, the input MUX switches back to the primary reference. When both primary and secondary references are detected as unavailable, the input MUX waits on secondary reference until either the primary or the secondary reference is detected as available again. In the case where both the primary and secondary reference inputs are detected as unavailable, LOS is active and the PLL outputs are automatically disabled. The timing diagram of an auto switch at the input MUX is shown in Figure 43.
R50[3-0] are the register bits that control the smart input MUX for PLL2 and PLL1, respectively, and can be programmed through I2C. Table 3 shows the input clock selection options for both PLLs that are supported through I2C programming and REFSEL pin.
R50.3 / R50.1 | R50.2 / R50.0 | REFSEL | MODE | PLL REFERENCE |
---|---|---|---|---|
0 | 0 | X | Automatic | PLL1 and/or PLL2 prefers primary |
0 | 1 | 0 | Manual | PLL1 selects primary, PLL2 select secondary |
0 | 1 | VIM | Manual | PLL1 prefers primary, PLL2 selects secondary |
0 | 1 | 1 | Automatic | PLL1 and PLL2 prefers primary |
1 | 0 | X | Manual | PLL1 and/or PLL2 selects primary |
1 | 1 | X | Manual | PLL1 and/or PLL2 selects secondary |
For those applications that require device start-up from a crystal on the secondary input, do a one-time only switchover to the primary input once available and, when auto switch on the PLLs’ smart MUXes are enabled, R51.2 can be set to 0 which automatically disables the secondary crystal input path after switchover to the primary input is complete. This removes coupling between the primary and secondary inputs and prevents input crosstalk components from appearing at the outputs. However, if the auto switch between primary and secondary is desired at any point of normal device operation, R51.2 should be set to 1, PLL should be set to a very low loop bandwidth, and R20, R21, and R22 should be set to 0x0 to ensure minimal phase hit once PLLs are relocked after switchover to either primary or secondary inputs. Figure 44 shows flowchart of events triggered when R51.2 is set to 1 or 0.