JAJSFA4E August 2015 – September 2024 LMK03328
PRODUCTION DATA
Before the outputs are enabled after power up, the LMK03328 goes through the initialization routine given in Table 10-2.
| PARAMETER | DEFINITION | DURATION | COMMENTS |
|---|---|---|---|
| TPWR | Step 1: Power up ramp | Depends on customer supply ramp time | The POR monitor holds the device in power-down/reset until the VDD supply voltage reaches 2.72 V (min) to 2.95 V (max) and VDDO_01 reaches 1.7 V (min). |
| TXO | Step 2: XO startup (if crystal is used) | Depends on XTAL. Can be several ms; For TXC 25-MHz typical XTAL start-up time measures 100 µs. | This step assumes PDN=1. The XTAL start-up time is the time XTAL takes to oscillate with sufficient amplitude. The LMK03328 has a built-in amplitude detection circuit, and halts the PLL lock sequence until the XTAL stage has sufficient swing. |
| TCAL-PLL1 | Step 3: Closed loop calibration period for PLL1 | Programmable cycles of internal 10-MHz oscillator. | This counter is needed for the PLL1 loop to stabilize. The duration can range from 30 µs to 300 ms. Recommended duration for PLL1 as clock generator (loop bandwidth > 10 kHz) is 300 µs and for PLL1 as jitter cleaner (loop bandwidth < 1 kHz) is 300 ms. |
| TVCO1 | Step 4: VCO1 wait period | Programmable cycles of internal 10-MHz oscillator. | This counter is needed for the VCO1 to stabilize. The duration can range from 20 µs to 200 ms. Recommended duration for VCO1 is 400 µs. |
| TLOCK-PLL1 | Step 5: PLL1 lock time | Approximately 4/LBW of PLL1 | The Outputs turn on immediately after calibration. A small frequency error remains for the duration of approximately 4/LBW (so in clock generator mode typically 10 µs for a PLL bandwidth of 400 kHz). The initial output frequency is lower than the target output frequency, as the loop filter starts out initially discharged. |
| TLOL-PLL1 | Step 6: PLL1 LOL indicator low | Approximately 1 PFD clock cycle | The PLL1 loss of lock indicator if selected on STATUS0 or STATUS1 goes low after 1 PFD clock cycle to indicate PLL1 is now locked. |
| TCAL-PLL2 | Step 7: Closed loop calibration period for PLL2 | Programmable cycles of internal 10-MHz oscillator. | This counter is needed for the PLL2 loop to stabilize. The duration can range from 30 µs to 300 ms. Recommended duration for PLL2 as clock generator (loop bandwidth > 10 kHz) is 300 µs and for PLL2 as jitter cleaner (loop bandwidth < 1 kHz) is 300 ms. |
| TVCO2 | Step 8: VCO2 wait period | Programmable cycles of internal 10-MHz oscillator. | This counter is needed for the VCO2 to stabilize. The duration can range from 20 µs to 200 ms. Recommended duration for VCO2 is 400 µs. |
| TLOCK-PLL2 | Step 9: PLL2 lock time | Approximately 4/LBW of PLL2 | The Outputs turn on immediately after calibration. A small frequency error remains for the duration of approximately 4/LBW (so in clock generator mode typically 10 µs for a PLL bandwidth of 400 kHz). The initial output frequency is lower than the target output frequency, as the loop filter starts out initially discharged. |
| TLOL-PLL2 | Step 10: PLL2 LOL indicator low | Approximately 1 PFD clock cycle | The PLL2 loss of lock indicator if selected on STATUS0 or STATUS1 goes low after 1 PFD clock cycle to indicate PLL2 is now locked. |
The LMK03328 start-up time for PLL1 or PLL2 is defined as the time taken, from the moment the core supplies reach 2.72 V and the VDDO_01 reaches 1.7 V, for either PLL to be locked and valid outputs are available at the outputs with no more than ±300-ppm error. Start-up time for PLL1 can be calculated as Equation 5.
When R12.1 = 0, start-up time for PLL2 can be calculated as Equation 6.
When R12.1 = 1, start-up time for PLL2 can be calculated as Equation 7.