Jitter-sensitive applications, such as the 10-Gbps or 100-Gbps Ethernet, deploy a serial link using a Serializer in the transmit section (TX) and a Deserializer in the receive section (RX). These SERDES blocks are typically embedded in an ASIC or FPGA. Estimating the clock jitter impact on the link budget requires an understanding of the TX PLL bandwidth and the RX CDR bandwidth.

As shown in Figure 10-1, the pass band region between the TX low-pass cutoff and RX high-pass cutoff frequencies is the range over what the reference clock jitter adds without any attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link attenuates the reference clock jitter with a 20 dB/dec or more steeper rolloff. Modern ASIC or FPGA designs have some flexibility on deciding the optimal RX CDR bandwidth and TX PLL bandwidth. These bandwidths are typically set based on what is achievable in the ASIC or FPGA process node, without increasing design complexity, and on any jitter tolerance or wander specification that must be met, as related to the RX CDR bandwidth.

The overall allowable jitter in a serial link is dictated by IEEE or other relevant standards. For example, IEEE802.3ba states that the maximum transmit jitter (peak-to-peak) for 10-Gbps Ethernet must be no more than 0.28 × UI, and this equates to a 27.1516 ps, pk-pk for the overall allowable transmit jitter.

The contributing elements of the jitter are the reference clock that is potentially generated from a device like LMK03328, the transmit medium, the transmit driver, and so forth. Only a portion of the overall allowable transmit jitter is allocated to the reference clock, which is typically 20% or lower. Therefore, the allowable reference clock jitter for a 20% clock jitter budget is 5.43 ps, pk-pk.

Jitter in a reference clock is composed of deterministic jitter that rises from spurious signals due to supply noise or mixing from other outputs or the reference input, along with random jitter that is typically due to thermal noise and other uncorrelated noise sources. A typical clock tree in a serial link system has clock generators and fan-out buffers. The allowable reference clock jitter of 5.43 ps, pk-pk is required at the output of the fan-out buffer.

Modern fan-out buffers have low additive random jitter (less than 100 fs, rms) with no substantial contribution to the deterministic jitter. Therefore, the clock generator and fan-out buffer contribute to the random jitter while the primary contributor to the deterministic jitter is the clock generator. The typical heuristic for modern clock generators is to allocate 25% of allowable reference clock jitter to the deterministic jitter and 75% to the random jitter. This jitter allocation amounts to an allowable deterministic jitter of 1.36 ps, pk-pk and an allowable random jitter of 4.07 ps, pk-pk. For serial link systems that must to meet a BER of 10^–12, the allowable random jitter in root-mean square is 0.29 ps, rms. These values are calculated by dividing the pk-pk jitter by 14 for a BER of 10^–12. Accounting for random jitter from the fan-out buffer, the random jitter required from the clock generator is 0.27 ps, rms. This random jitter value is calculated by the root-mean square subtraction from the desired jitter at the output of the fan-out buffer, assuming there is 100 fs, rms of additive jitter from the fan-out buffer.

With careful frequency planning techniques, like spur optimization (covered in the Spur Mitigation Techniques section) and on-chip LDOs to suppress supply noise, the LMK03328 is able to generate clock outputs with deterministic jitter that is below 1 ps, pk-pk, and random jitter that is below 0.2 ps, rms. This jitter performance gives the serial link system an additional margin on the allowable transmit jitter, which results in a BER better than 10^–12.

Figure 10-1 Dependence of Clock Jitter in Serial Links