JAJSF03K September 2011 – December 2023 LMK03806
PRODUCTION DATA
The tools listed above automatically configure the clock solution to meet the input and output frequency requirements given and make assumptions about certain parameters to give default simulation results. The assumptions made are to maximize input frequencies, Fpd, and charge pump currents while minimizing Fvco and divider values. We will also outline the steps for manually configuring the device below for greater flexibility. Note that this procedure is the same as the one outlined in the Frequency Planning With the LMK03806 and Configuring the PLL sections, which can be referenced for a more detailed explanation.
We are given the target output frequencies of 156.25 MHz, 125 MHz, 100 MHz, and 25 MHz with an FOSCin of 20 MHz. As previously calculated, the LCM and Fvco is 2500 MHz.
First, we will consider the PLL reference path. For lowest possible in-band PLL flat noise, we will try to maximize Fpd. 20 MHz is the highest frequency which divides into 2500 MHz by an integer value and which can also be synthesized from FOSCin. As noted earlier, when FOSCin and fpd are equal, the best PLL in-band noise can be achieved with the PLL reference doubler enabled (EN_PLL_REF_2X=1) and the PLL reference divider is 2 (PLL_R =2).
Next, we will consider the PLL feedback path. As determined earlier, Fvco is 2500 MHz and the Fpd is 20 MHz, which is 2500 MHz divided by 125. The prescaler and N divider settings together must divide Fvco by 125. The only setting that works in this case is a prescaler value of 5 and an N divider value of 25.
At this point the design meets all input and output frequency requirements and it is possible to design a loop filter for the application and simulate phase noise of the output clocks.