Crystal input to OSCin pins (purple circle):
- Place crystal with associated load capacitors (C6 and C9) as close as possible to the chip, and use short/direct routing to the OSCin pins.
- If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the device are placed. In this area, avoid using vias in the crystal signal path and routing other signals below the crystal paths, as these could be potential areas for noise coupling.
Clock outputs (blue circles):
- Differential signals should be routed tightly coupled to minimize PCB crosstalk. Trace impedance and loading/terminations should be designed according to output type being used (that is, LVDS, LVPECL...).
- Unused output pins should be left open without connection to a trace. Unused outputs should be powered down through registers to reduce power and switching noise.
Power pins (green rectangles):
- Place ferrite beads and bypass caps as close as possible to the Vcc pins as possible. Design a low impedance power distribution network over a wide frequency range using multiple decoupling and bypass caps with different values/sizes. Use ferrite beads to isolate the device supply pins from board noise sources.
Loop filter (orange oval):
- Place loop filter resistor and capacitors nearby the chip, and route loop filter nodes from digital traces or noisy power traces/planes to avoid noise coupling.