At this time, the user may choose to use the simulation tools for more accurate simulations. For example:
- Clock Design Tool allows loading a custom phase noise profile for various blocks. Typically, a custom phase noise plot is entered for OSCin to match the reference phase noise to the device. For improved accuracy in simulation and optimum loop filter design, be sure to load these custom noise profiles for use in application. After loading a phase noise plot, user should recalculate the recommended loop filter design.
- The Clock Design Tool will return solutions with high reference/phase detector frequencies by default. In the Clock Design Tool the user may increase the reference divider to reduce the frequency if desired. For example, if a narrow loop bandwidth is desired, it is possible to reduce Fpd by increasing the PLL R divider.
Note: Clock Design Tool provides some recommended loop filters upon first loading the simulation. These values are not re-calculated any time PLL related values are changed (for example, input phase noise, charge pump current, divider values, etc.), so it is recommended to re-design the PLL loop filter, either by manually entering desired values, or by using the ‘Design a Loop Filter’ button in the LOOPFILTER box.