JAJSF03K September 2011 – December 2023 LMK03806
PRODUCTION DATA
The clock output types of the LMK03806 are individually programmable. The CLKoutX_TYPE registers set the output type of an individual clock output to LVDS, LVPECL, LVCMOS, or powers down the output buffer. Note that LVPECL supports four different amplitude levels and LVCMOS supports single LVCMOS outputs, inverted, and normal polarity of each output pin for maximum flexibility.
The programming addresses table shows at what register and address the specified clock output CLKoutX_TYPE register is located.
The CLKoutX_TYPE table shows the programming definition for these registers.
CLKoutX | PROGRAMMING ADDRESS |
---|---|
CLKout0 | R6[19:16] |
CLKout1 | R6[23:20] |
CLKout2 | R6[27:24] |
CLKout3 | R6[31:28] |
CLKout4 | R7[19:16] |
CLKout5 | R7[23:20] |
CLKout6 | R7[27:24] |
CLKout7 | R7[31:28] |
CLKout8 | R8[19:16] |
CLKout9 | R8[23:20] |
CLKout10 | R8[27:24] |
CLKout11 | R8[31:28] |
R6-R8[31:28, 27:24, 23:20] | DEFINITION |
---|---|
0 (0x00) | Powerdown |
1 (0x01) | LVDS |
2 (0x02) | LVPECL (700 mVpp) |
3 (0x03) | LVPECL (1200 mVpp) |
4 (0x04) | LVPECL (1600 mVpp) |
5 (0x05) | LVPECL (2000 mVpp) |
6 (0x06) | LVCMOS (Norm/Inv) |
7 (0x07) | LVCMOS (Inv/Norm) |
8 (0x08) (1) | LVCMOS (Norm/Norm) |
9 (0x09) (1) | LVCMOS (Inv/Inv) |
10 (0x0A) (1) | LVCMOS (Low/Norm) |
11 (0x0A) (1) | LVCMOS (Low/Inv) |
12 (0x0C) (1) | LVCMOS (Norm/Low) |
13 (0x0D) (1) | LVCMOS (Inv/Low) |
14 (0x0E) (1) | LVCMOS (Low/Low) |