JAJSF03K September   2011  – December 2023 LMK03806

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Features Description
      1. 7.3.1 Serial MICROWIRE Timing Diagram and Terminology
      2. 7.3.2 Crystal Support With Buffered Outputs
      3. 7.3.3 Integrated Loop Filter Poles
      4. 7.3.4 Integrated VCO
      5. 7.3.5 Clock Distribution
        1. 7.3.5.1 CLKout DIvider
        2. 7.3.5.2 Programmable Output Type
        3. 7.3.5.3 Clock Output Synchronization
      6. 7.3.6 Default Start-Up Clocks
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 General Information
        1. 7.5.1.1 Special Programming Case for R0 to R5 for CLKoutX_Y_DIV > 25
        2. 7.5.1.2 Recommended Initial Programming Sequence
        3. 7.5.1.3 READBACK
          1. 7.5.1.3.1 Readback Example
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Crystal Interface
      2. 8.1.2 Driving OSCin Pins With a Single-Ended Source
      3. 8.1.3 Driving OSCin Pins With a Differential Source
      4. 8.1.4 Frequency Planning With the LMK03806
      5. 8.1.5 Configuring the PLL
        1. 8.1.5.1 Example PLL Configuration
      6. 8.1.6 Digital Lock Detect
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Device Selection
          1. 8.2.2.1.1 Clock Architect
          2. 8.2.2.1.2 Clock Design Tool
          3. 8.2.2.1.3 Calculation Using LCM
        2. 8.2.2.2 Device Configuration
        3. 8.2.2.3 PLL Loop Filter Design
          1. 8.2.2.3.1 Example Loop Filter Design
        4. 8.2.2.4 Other Device Specific Configuration
          1. 8.2.2.4.1 Digital Lock Detect
        5. 8.2.2.5 Device Programming
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 System Level Diagram
    4. 8.4 Best Design Practices
      1. 8.4.1 LVCMOS Complementary vs. Non-Complementary Operation
      2. 8.4.2 LVPECL Outputs
      3. 8.4.3 Sharing MICROWIRE (SPI) Lines
      4. 8.4.4 SYNC Pin
      5. 8.4.5 CLKout Vcc Pins
    5. 8.5 Power Supply Recommendations
      1. 8.5.1 Current Consumption and Power Dissipation Calculations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Register Maps
    1. 10.1  Default Device Register Settings After Power On Reset
    2. 10.2  Register R0 TO R5
      1. 10.2.1 CLKoutX_Y_PD, Powerdown CLKoutX_Y Output Path
      2. 10.2.2 RESET
      3. 10.2.3 POWERDOWN
      4. 10.2.4 CLKoutX_Y_DIV, Clock Output Divide
    3. 10.3  Registers R6 TO R8
      1. 10.3.1 CLKoutX_TYPE
    4. 10.4  REGISTER R9
    5. 10.5  REGISTER R10
      1. 10.5.1 OSCout1_TYPE, LVPECL Output Amplitude Control
      2. 10.5.2 OSCout0_TYPE
      3. 10.5.3 EN_OSCoutX, OSCout Output Enable
      4. 10.5.4 OSCoutX_MUX, Clock Output Mux
      5. 10.5.5 OSCout_DIV, Oscillator Output Divide
    6. 10.6  REGISTER R11
      1. 10.6.1 NO_SYNC_CLKoutX_Y
      2. 10.6.2 SYNC_POL_INV
      3. 10.6.3 SYNC_TYPE
      4. 10.6.4 EN_PLL_XTAL
    7. 10.7  REGISTER R12
      1. 10.7.1 LD_MUX
      2. 10.7.2 LD_TYPE
      3. 10.7.3 SYNC_PLL_DLD
    8. 10.8  REGISTER R13
      1. 10.8.1 READBACK_TYPE
      2. 10.8.2 GPout0
    9. 10.9  REGISTER 14
      1. 10.9.1 GPout1
    10. 10.10 REGISTER 16
    11. 10.11 REGISTER 24
      1. 10.11.1 PLL_C4_LF, PLL Integrated Loop Filter Component
      2. 10.11.2 PLL_C3_LF, PLL Integrated Loop Filter Component
      3. 10.11.3 PLL_R4_LF, PLL Integrated Loop Filter Component
      4. 10.11.4 PLL_R3_LF, PLL Integrated Loop Filter Component
    12. 10.12 REGISTER 26
      1. 10.12.1 EN_PLL_REF_2X, PLL Reference Frequency Doubler
      2. 10.12.2 PLL_CP_GAIN, PLL Charge Pump Current
      3. 10.12.3 PLL_DLD_CNT
    13. 10.13 REGISTER 28
      1. 10.13.1 PLL_R, PLL R Divider
    14. 10.14 REGISTER 29
      1. 10.14.1 OSCin_FREQ, PLL Oscillator Input Frequency Register
      2. 10.14.2 PLL_N_CAL, PLL N Calibration Divider
    15. 10.15 REGISTER 30
      1. 10.15.1 PLL_P, PLL N Prescaler Divider
      2. 10.15.2 PLL_N, PLL N Divider
    16. 10.16 REGISTER 31
      1. 10.16.1 READBACK_ADDR
      2. 10.16.2 uWire_LOCK
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Detailed Design Procedure

Design of all aspects of the LMK03806 is quite involved and software has been written to assist in part selection, part programming, loop filter design, and simulation. This design procedure will give a quick outline of the process.

Note:

This information is current as of the date of the release of this data sheet. Design tools receive continuous enhancements to add features and improve model accuracy. Refer to software instructions or training for latest features.

  1. Device Selection
    • The key to device selection is the required Fvco given the required output frequencies. The device must be able to produce a Fvco that can be divided down to required output frequencies.
    • The software design tools will take into account the Fvco range for specific devices based on the application's required output frequencies.
  2. Device Configuration
    • There are many possible permutations of dividers and other registers to get same output frequencies from a device. However there are some optimizations and trade-offs to be considered.
      • If more than one divider is in series, for instance PLL prescaler followed by PLL N divider, it is possible although not assured that some crosstalk/mixing could be created when using some divides.
    • The design software normally attempts to maximize Fpd, use smallest dividers, and maximize PLL charge pump current.
    • Refer to Configuring the PLL for divider equations to ensure the PLL is locked. The design software is able to configure the device for most cases.
    • These guidelines may be followed when configuring PLL related dividers or other related registers:
      • For lowest possible in-band PLL flat noise, maximize Fpd to minimize N divide value.
      • For lowest possible in-band PLL flat noise, maximize charge pump current. Higher value charge pump currents often yield similar performance.
      • To reduce loop filter component sizes, increase the total feedback divide value (PLL_P × PLL_N) and/or reduce charge pump current.
      • As rule of thumb, keep Fpd approximately between 10 × PLL loop bandwidth and 100 × PLL loop bandwidth. An Fpd value less than 5 × PLL bandwidth may be unstable and a Fpd > 100 × loop bandwidth may experience increased lock time due to cycle slipping.
  3. PLL Loop Filter Design
    • TI recommends to use Clock Design Tool or Clock Architect to design your loop filter.
    • The Clock Design Tool will return solutions with high reference/phase detector frequencies by default. In the Clock Design Tool the user may choose to increase the reference divider to reduce the Fpd to achieve a narrow loop bandwidth, so it is possible to reduce loop filter capacitor to a practical value.
    • While designing the loop filter, adjusting the charge pump current and/or the total feedback divide value (PLL_P × PLL_N) can help with loop filter component selection. Lower charge pump currents and larger N values result in smaller loop filter capacitor values but at the expense of increased in-band PLL phase noise.
    • More detailed understanding of PLL loop filter design can found in PLL Performance, Simulation, and Design (www.ti.com/tool/pll_book).
  4. Clock Output Assignment
    • At this point of time, the design software does not take into account frequency assignment to specific outputs except to ensure that the output frequencies can be achieved. It is best to consider proximity of each clock output to each other and other PLL circuitry when choosing final clock output locations. Here are some guidelines to help achieve best performance when assigning outputs to specific CLKout/OSCout pins.
      • Group common frequencies together.
      • PLL charge pump circuitry can cause crosstalk at charge pump frequency. Place outputs sharing charge pump frequency or lower priority outputs that are not sensitive to charge pump frequency spurs together.
  5. Other device specific configuration. For LMK03806 consider the following:
    • PLL digital lock detect based on programming:
      • There is a digital lock detect circuit which is used to determine the lock status of the PLL. It can also be used to ensure a specific frequency accuracy. A user specified frequency accuracy required to trigger a lock detect event is programmable using a lock count register. Refer to Digital Lock Detect for more information.
  6. Device Programming
    • The software tool CodeLoader for EVM programming can be used to set up the device in the desired configuration, then export a hex register map suitable for use in application. Some additional information on each part of the design procedure for the example is outlined below.