LMK04208は高性能のクロック・コンディショナーであり、高度な機能によってクロックの生成、分配、ジッタのクリーニングに優れた性能を発揮し、次世代システムの要件を満たします。デュアル・ループ PLLatinum™アーキテクチャにより、低ノイズのVCXOモジュールを使用して111 fsのRMSジッタ(12kHz~20MHz)、または低コストの外付け水晶振動子およびバラクタ・ダイオードを使用して200fs以下のRMSジッタ(12kHz~20MHz)を実現できます。
デュアル・ループ・アーキテクチャは、2つの高性能な位相調整されたループ(PLL)、低ノイズの水晶発振器回路、高性能な電圧制御発振器(VCO)で構成されます。最初のPLL (PLL1)は低ノイズのジッタ・クリーナ機能を提供し、2番目のPLL (PLL2)はクロック生成を行います。PLL1は、外付けのVCXOモジュール、または内蔵の水晶発振器と外付けの調整可能水晶振動子およびバラクタ・ダイオードとともに動作するよう構成できます。非常に狭いループ帯域幅と組み合わせた場合、PLL1はVCXOモジュールまたは調整可能水晶振動子の優れたクローズイン位相ノイズ(50kHzより低いオフセット)を使用して、入力クロックをクリーニングします。PLL1の出力は、PLL2へのクリーンな基準入力として使用され、内蔵のVCOをロックします。PLL2のループ帯域幅は、ファーアウト位相ノイズ(50kHzよりも高いオフセット)をクリーニングするよう最適化でき、この場合は内蔵のVCOが、PLL1で使用されているVCXOモジュールや調整可能水晶振動子よりも高性能になります。
型番 | VCO周波数 | クロック入力 |
---|---|---|
LMK04208 | 2750~3072MHz | 2 |
日付 | 改訂内容 | 注 |
---|---|---|
2016年9月 | * | 初版 |
PIN | I/O | TYPE | DESCRIPTION | |
---|---|---|---|---|
NO. | NAME | |||
1, 2 | NC | – | – | No Connection. These pins must be left floating. |
3, 4 | CLKout0*, CLKout0 | O | Programmable | Clock output 0. |
5 | NC | – | – | No Connection. These pins must be left floating. |
6 | SYNC | I/O | Programmable | CLKout Synchronization input or programmable status pin. |
7, 8, 9 | NC | – | – | No Connection. These pins must be left floating. |
10 | Vcc1 | PWR | Power supply for VCO LDO. | |
11 | LDObyp1 | ANLG | LDO Bypass, bypassed to ground with 10-µF capacitor. | |
12 | LDObyp2 | ANLG | LDO Bypass, bypassed to ground with a 0.1-µF capacitor. | |
13, 14 | CLKout1, CLKout1* | O | Programmable | Clock output 1. |
15, 16 | NC | – | – | No Connection. These pins must be left floating. |
17 | Vcc2 | PWR | Power supply for clock output 1. | |
18 | Vcc3 | PWR | Power supply for clock output 2. | |
19, 20 | NC | – | – | No Connection. These pins must be left floating. |
21, 22 | CLKout2*, CLKout2 | O | Programmable | Clock output 2. |
23 | GND | PWR | Ground. | |
24 | Vcc4 | PWR | Power supply for digital. | |
25, 26 | CLKin1, CLKin1* | I | ANLG | Reference Clock Input Port 1 for PLL1. AC or DC Coupled. |
FBCLKin, FBCLKin* | Feedback input for external clock feedback input (0-delay mode). AC or DC Coupled. | |||
Fin/Fin* | External VCO input (External VCO mode). AC or DC Coupled. | |||
27 | Status_Holdover | I/O | Programmable | Programmable status pin, default readback output. Programmable to holdover mode indicator. Other options available by programming. |
28, 29 | CLKin0, CLKin0* | I | ANLG | Reference Clock Input Port 0 for PLL1. AC or DC Coupled. |
30 | Vcc5 | PWR | Power supply for clock inputs. | |
31, 32 | NC | – | – | No Connection. These pins must be left floating. |
33 | Status_LD | I/O | Programmable | Programmable status pin, default lock detect for PLL1 and PLL2. Other options available by programming. |
34 | CPout1 | O | ANLG | Charge pump 1 output. |
35 | Vcc6 | PWR | Power supply for PLL1, charge pump 1. | |
36, 37 | OSCin, OSCin* | I | ANLG | Feedback to PLL1, Reference input to PLL2. AC Coupled. |
38 | Vcc7 | PWR | Power supply for OSCin, OSCout, and PLL2 circuitry.(2) | |
39, 40 | OSCout, OSCout* | O | Programmable | Buffered output of OSCin port.(2) |
41 | Vcc8 | PWR | Power supply for PLL2, charge pump 2. | |
42 | CPout2 | O | ANLG | Charge pump 2 output. |
43 | Vcc9 | PWR | Power supply for PLL2. | |
44 | LEuWire | I | CMOS | MICROWIRE Latch Enable Input. |
45 | CLKuWire | I | CMOS | MICROWIRE Clock Input. |
46 | DATAuWire | I | CMOS | MICROWIRE Data Input. |
47 | Vcc10 | PWR | Power supply for clock output 3. | |
48, 49 | CLKout3, CLKout3* | O | Programmable | Clock output 3. |
50, 51 | NC | – | – | No Connection. These pins must be left floating. |
52 | Vcc11 | PWR | Power supply for clock output 4. | |
53, 54 | CLKout4, CLKout4* | O | Programmable | Clock output 4. |
55, 56 | NC | – | – | No Connection. These pins must be left floating. |
57 | Vcc12 | PWR | Power supply for clock output 5. | |
58, 59 | CLKout5, CLKout5* | O | Programmable | Clock output 5. |
60, 61 | NC | – | – | No Connection. These pins must be left floating. |
62 | Status_CLKin0 | I/O | Programmable | NC. Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin0 LOS status and other options available by programming. |
63 | Status_CLKin1 | I/O | Programmable | Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin1 LOS status and other options available by programming. |
64 | Vcc13 | PWR | Power supply for clock output 0. | |
DAP | DAP | – | GND | DIE ATTACH PAD, connect to GND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Supply voltage (2) | –0.3 | 3.6 | V |
VIN | Input voltage | –0.3 | VCC + 0.3 | V |
TL | Lead temperature (solder 4 seconds) | 260 | °C | |
TJ | Junction temperature | 150 | °C | |
IIN | Differential input current (CLKinX/X*, OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*) |
± 5 | mA | |
MSL | Moisture Sensitivity Level | 3 | ||
Tstg | Storage temperature | -65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
TJ | Junction temperature | 125 | °C | |||
TA | Ambient temperature | VCC = 3.3 V | –40 | 25 | 85 | °C |
VCC | Supply voltage | 3.15 | 3.3 | 3.45 | V |
THERMAL METRIC(1) | LMK04208 | UNIT | |
---|---|---|---|
NKD (WQFN) | |||
64 PINS | |||
RθJA | Junction-to-ambient thermal resistance on 4-layer JEDEC PCB(2)(8) | 25.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance(3)(9) | 6.9 | °C/W |
RθJB | Junction-to-board thermal resistance(4) | 4.0 | °C/W |
ψJT | Junction-to-top characterization parameter(5) | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter(6) | 4.0 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance(7) | 0.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CURRENT CONSUMPTION | ||||||
ICC_PD | Power down supply current | 1 | 3 | mA | ||
ICC_CLKS | Supply current with all clocks (CLKoutX) and OSCout enabled as LVDS.(2) | All clock delays disabled, CLKoutX_DIV = 1045, EN_SYNC=0 PLL1 and PLL2 locked. |
445 | 535 | mA | |
CLKin0/0* and CLKin1/1* INPUT CLOCK SPECIFICATIONS | ||||||
fCLKin | Clock input frequency(3) | 0.001 | 500 | MHz | ||
SLEWCLKin(4) | Clock input slew rate(17) | 20% to 80% | 0.15 | 0.5 | V/ns | |
VIDCLKin | Clock input Differential input voltage (see (1) and Figure 8) |
AC coupled CLKinX_BUF_TYPE = 0 (Bipolar) |
0.25 | 1.55 | |V| | |
VSSCLKin | 0.5 | 3.1 | Vpp | |||
VIDCLKin | AC coupled CLKinX_BUF_TYPE = 1 (MOS) |
0.25 | 1.55 | |V| | ||
VSSCLKin | 0.5 | 3.1 | Vpp | |||
VCLKin | Clock input Single-ended input voltage(17) |
AC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_BUF_TYPE = 0 (Bipolar) |
0.25 | 2.4 | Vpp | |
AC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_BUF_TYPE = 1 (MOS) |
0.25 | 2.4 | Vpp | |||
VCLKin0-offset | DC offset voltage between CLKin0/CLKin0* CLKin0* - CLKin0 |
Each pin AC coupled CLKin0_BUF_TYPE = 0 (Bipolar) |
20 | mV | ||
VCLKin1-offset | DC offset voltage between CLKin1/CLKin1* CLKin1* - CLKin1 |
0 | mV | |||
VCLKinX-offset | DC offset voltage between CLKinX/CLKinX* CLKinX* - CLKinX |
Each pin AC coupled CLKinX_BUF_TYPE = 1 (MOS) |
55 | mV | ||
VCLKin- VIH | High input voltage | DC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_BUF_TYPE = 1 (MOS) |
2.0 | VCC | V | |
VCLKin- VIL | Low input voltage | 0.0 | 0.4 | V | ||
FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS | ||||||
fFBCLKin | Clock input frequency(17) | AC coupled (CLKinX_BUF_TYPE = 0) MODE = 2 or 8; FEEDBACK_MUX = 6 |
0.001 | 1000 | MHz | |
fFin | Clock input frequency(17) | AC coupled (CLKinX_BUF_TYPE = 0) MODE = 3 or 11 |
0.001 | 3100 | MHz | |
VFBCLKin/Fin | Single Ended Clock input voltage(17) |
AC coupled; (CLKinX_BUF_TYPE = 0) |
0.25 | 2.0 | Vpp | |
SLEWFBCLKin/Fin | Slew rate on CLKin(17)(4) | AC coupled; 20% to 80%; (CLKinX_BUF_TYPE = 0) |
0.15 | 0.5 | V/ns | |
PLL1 SPECIFICATIONS | ||||||
fPD1 | PLL1 phase detector frequency | 40 | MHz | |||
ICPout1SOURCE | PLL1 charge Pump source current(5) |
VCPout1 = VCC/2, PLL1_CP_GAIN = 0 | 100 | µA | ||
VCPout1 = VCC/2, PLL1_CP_GAIN = 1 | 200 | |||||
VCPout1 = VCC/2, PLL1_CP_GAIN = 2 | 400 | |||||
VCPout1 = VCC/2, PLL1_CP_GAIN = 3 | 1600 | |||||
ICPout1SINK | PLL1 charge Pump sink current(5) |
VCPout1=VCC/2, PLL1_CP_GAIN = 0 | –100 | µA | ||
VCPout1=VCC/2, PLL1_CP_GAIN = 1 | –200 | |||||
VCPout1=VCC/2, PLL1_CP_GAIN = 2 | –400 | |||||
VCPout1=VCC/2, PLL1_CP_GAIN = 3 | –1600 | |||||
ICPout1%MIS | Charge pump Sink/source mismatch |
VCPout1 = VCC/2, T = 25 °C | 3% | 10% | ||
ICPout1VTUNE | Magnitude of charge pump current variation vs. charge pump voltage | 0.5 V < VCPout1 < VCC - 0.5 V TA = 25 °C |
4% | |||
ICPout1%TEMP | Charge pump current vs. temperature variation |
4% | ||||
ICPout1 TRI | Charge Pump TRI-STATE leakage current | 0.5 V < VCPout < VCC - 0.5 V | 5 | nA | ||
PN10kHz | PLL 1/f noise at 10 kHz offset.(9) Normalized to 1 GHz Output Frequency | PLL1_CP_GAIN = 400 µA | –117 | dBc/Hz | ||
PLL1_CP_GAIN = 1600 µA | –118 | |||||
PN1Hz | Normalized phase noise contribution(10) | PLL1_CP_GAIN = 400 µA | –221.5 | dBc/Hz | ||
PLL1_CP_GAIN = 1600 µA | –223 | |||||
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS | ||||||
fOSCin | PLL2 reference input(6) | 500 | MHz | |||
SLEWOSCin | PLL2 reference clock minimum slew rate on OSCin(17) | 20% to 80% | 0.15 | 0.5 | V/ns | |
VOSCin | Input voltage for OSCin or OSCin*(17) | AC coupled; Single-ended (Unused pin AC coupled to GND) | 0.2 | 2.4 | Vpp | |
VIDOSCin | Differential voltage swing (see Figure 8) | AC coupled | 0.2 | 1.55 | |V| | |
VSSOSCin | 0.4 | 3.1 | Vpp | |||
VOSCin-offset | DC offset voltage between OSCin/OSCin* OSCinX* - OSCinX |
Each pin AC coupled | 20 | mV | ||
fdoubler_max | Doubler input frequency(17) | EN_PLL2_REF_2X = 1;(7)
OSCin Duty Cycle 40% to 60% |
155 | MHz | ||
CRYSTAL OSCILLATOR MODE SPECIFICATIONS | ||||||
fXTAL | Crystal frequency range(17) | RESR < 40 Ω | 6 | 20.5 | MHz | |
PXTAL | Crystal power dissipation(8) | Vectron VXB1 crystal, 20.48 MHz, RESR < 40 Ω XTAL_LVL = 0 |
100 | µW | ||
CIN | Input capacitance of LMK04208 OSCin port |
-40 to +85 °C | 6 | pF | ||
PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS | ||||||
fPD2 | Phase detector frequency | 155 | MHz | |||
ICPoutSOURCE | PLL2 charge pump source current(5) | VCPout2=VCC/2, PLL2_CP_GAIN = 0 | 100 | µA | ||
VCPout2=VCC/2, PLL2_CP_GAIN = 1 | 400 | |||||
VCPout2=VCC/2, PLL2_CP_GAIN = 2 | 1600 | |||||
VCPout2=VCC/2, PLL2_CP_GAIN = 3 | 3200 | |||||
ICPoutSINK | PLL2 charge pump sink current(5) | VCPout2=VCC/2, PLL2_CP_GAIN = 0 | –100 | µA | ||
VCPout2=VCC/2, PLL2_CP_GAIN = 1 | –400 | |||||
VCPout2=VCC/2, PLL2_CP_GAIN = 2 | –1600 | |||||
VCPout2=VCC/2, PLL2_CP_GAIN = 3 | –3200 | |||||
ICPout2%MIS | Charge pump sink/source mismatch | VCPout2=VCC/2, TA = 25 °C | 3% | 10% | ||
ICPout2VTUNE | Magnitude of charge pump current vs. charge pump voltage variation | 0.5 V < VCPout2 < VCC - 0.5 V TA = 25 °C |
4% | |||
ICPout2%TEMP | Charge pump current vs. Temperature variation |
4% | ||||
ICPout2TRI | Charge pump leakage | 0.5 V < VCPout2 < VCC - 0.5 V | 10 | nA | ||
PN10kHz | PLL 1/f Noise at 10 kHz offset(9)
Normalized to 1 GHz output frequency |
PLL2_CP_GAIN = 400 µA | –118 | dBc/Hz | ||
PLL2_CP_GAIN = 3200 µA | –121 | |||||
PN1Hz | Normalized Phase Noise Contribution(10) | PLL2_CP_GAIN = 400 µA | –222.5 | dBc/Hz | ||
PLL2_CP_GAIN = 3200 µA | –227 | |||||
INTERNAL VCO SPECIFICATIONS | ||||||
fVCO | VCO tuning range | LMK04208 | 2750 | 3072 | MHz | |
KVCO | Fine tuning sensitivity (The range displayed in the typical column indicates the lower sensitivity is typical at the lower end of the tuning range, and the higher tuning sensitivity is typical at the higher end of the tuning range). |
LMK04208 | 20 to 36 | MHz/V | ||
|ΔTCL| | Allowable Temperature Drift for Continuous Lock(11) (17) | After programming R30 for lock, no changes to output configuration are permitted to ensure continuous lock | 125 | °C | ||
CLKout CLOSED LOOP JITTER SPECIFICATIONS USING a COMMERCIAL QUALITY VCXO(14) | ||||||
L(f)CLKout | LMK04208 fCLKout = 245.76 MHz SSB Phase noise Measured at clock outputs Value is average for all output types(12) |
Offset = 1 kHz | –122.5 | dBc/Hz | ||
Offset = 10 kHz | –132.9 | |||||
Offset = 100 kHz | –135.2 | |||||
Offset = 800 kHz | –143.9 | |||||
Offset = 10 MHz; LVDS | –156.0 | |||||
Offset = 10 MHz; LVPECL 1600 mVpp | –157.5 | |||||
Offset = 10 MHz; LVCMOS | –157.1 | |||||
JCLKout
LVDS/LVPECL/LVCMOS |
LMK04208(12)
fCLKout = 245.76 MHz Integrated RMS jitter |
BW = 12 kHz to 20 MHz | 111 | fs, RMS | ||
BW = 100 Hz to 20 MHz | 123 | |||||
CLKout CLOSED LOOP JITTER SPECIFICATIONS USING THE INTEGRATED LOW NOISE CRYSTAL OSCILLATOR CIRCUIT (15) | ||||||
LMK04208 fCLKout = 245.76 MHz Integrated RMS jitter |
BW = 12 kHz to 20 MHz XTAL_LVL = 3 |
192 | fs rms | |||
BW = 100 Hz to 20 MHz XTAL_LVL = 3 |
450 | |||||
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY | ||||||
fCLKout-startup | Default output clock frequency at device power on(16) | CLKout4, LVDS, LMK04208 | 90 | 110 | 130 | MHz |
CLOCK SKEW and DELAY | ||||||
|TSKEW| | Maximum CLKoutX to CLKoutY(17)(13) | LVDS-to-LVDS, T = 25 °C, FCLK = 800 MHz, RL= 100 Ω AC coupled |
30 | ps | ||
LVPECL-to-LVPECL, T = 25 °C, FCLK = 800 MHz, RL= 100 Ω emitter resistors = 240 Ω to GND AC coupled |
30 | |||||
Maximum skew between any two LVCMOS outputs, same CLKout or different CLKout(17)(13) | RL = 50 Ω, CL = 5 pF, T = 25 °C, FCLK = 100 MHz. |
100 | ||||
MixedTSKEW | LVDS or LVPECL to LVCMOS | Same device, T = 25 °C, 250 MHz |
750 | ps | ||
td0-DELAY | CLKin to CLKoutX delay(13) | MODE = 2 PLL1_R_DLY = 0; PLL1_N_DLY = 0 |
1850 | ps | ||
MODE = 2 PLL1_R_DLY = 0; PLL1_N_DLY = 0; VCO Frequency = 2949.12 MHz Analog delay select = 0; Feedback clock digital delay = 11; Feedback clock half step = 1; Output clock digital delay = 5; Output clock half step = 0; |
0 | |||||
LVDS CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 1 | ||||||
fCLKout | Maximum frequency(17)(18) | RL = 100 Ω | 1536 | MHz | ||
VOD | Differential output voltage (see Figure 9) | T = 25 °C, DC measurement AC coupled to receiver input R = 100-Ω differential termination |
250 | 400 | 450 | |mV| |
VSS | 500 | 800 | 900 | mVpp | ||
ΔVOD | Change in magnitude of VOD for complementary output states | –50 | 50 | mV | ||
VOS | Output offset voltage | 1.125 | 1.25 | 1.375 | V | |
ΔVOS | Change in VOS for complementary output states | 35 | |mV| | |||
TR / TF | Output rise time | 20% to 80%, RL = 100 Ω | 200 | ps | ||
Output fall time | 80% to 20%, RL = 100 Ω | |||||
ISA
ISB |
Output short circuit current single-ended |
Single-ended output shorted to GND T = 25 °C |
–24 | 24 | mA | |
ISAB | Output short circuit current - differential | Complimentary outputs tied together | –12 | 12 | mA | |
LVPECL CLOCK OUTPUTS (CLKoutX) | ||||||
fCLKout | Maximum frequency(17)(18) | 1536 | MHz | |||
TR / TF | 20% to 80% output rise | RL = 100 Ω, emitter resistors = 240 Ω to GND CLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp) |
150 | ps | ||
80% to 20% output fall time | ||||||
700-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 2 | ||||||
VOH | Output high voltage | T = 25 °C, DC measurement Termination = 50 Ω to VCC - 1.4 V |
VCC – 1.03 | V | ||
VOL | Output low voltage | VCC – 1.41 | V | |||
VOD | Output voltage (see Figure 9) | 305 | 380 | 440 | |mV| | |
VSS | 610 | 760 | 880 | mVpp | ||
1200-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 3 | ||||||
VOH | Output high voltage | T = 25 °C, DC measurement Termination = 50 Ω to VCC - 1.7 V |
VCC – 1.07 | V | ||
VOL | Output low voltage | VCC – 1.69 | V | |||
VOD | Output voltage (see Figure 9) | 545 | 625 | 705 | |mV| | |
VSS | 1090 | 1250 | 1410 | mVpp | ||
1600-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 4 | ||||||
VOH | Output high voltage | T = 25 °C, DC Measurement Termination = 50 Ω to VCC - 2.0 V |
VCC – 1.10 | V | ||
VOL | Output low voltage | VCC – 1.97 | V | |||
VOD | Output voltage (see Figure 9) | 660 | 870 | 965 | |mV| | |
VSS | 1320 | 1740 | 1930 | mVpp | ||
2000-mVpp LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 5 | ||||||
VOH | Output high voltage | T = 25 °C, DC Measurement Termination = 50 Ω to VCC - 2.3 V |
VCC – 1.13 | V | ||
VOL | Output low voltage | VCC – 2.20 | V | |||
VOD | Output voltage Figure 9 | 800 | 1070 | 1200 | |mV| | |
VSS | 1600 | 2140 | 2400 | mVpp | ||
LVCMOS CLOCK OUTPUTS (CLKoutX) | ||||||
fCLKout | Maximum frequency(17)(18) | 5 pF Load | 250 | MHz | ||
VOH | Output high voltage | 1 mA Load | VCC – 0.1 | V | ||
VOL | Output low voltage | 1 mA Load | 0.1 | V | ||
IOH | Output high current (source) | VCC = 3.3 V, VO = 1.65 V | 28 | mA | ||
IOL | Output low current (sink) | VCC = 3.3 V, VO = 1.65 V | 28 | mA | ||
DUTYCLK | Output duty cycle(17) | VCC/2 to VCC/2, FCLK = 100 MHz T = 25 °C |
45% | 50% | 55% | |
TR | Output rise time | 20% to 80%, RL = 50 Ω, CL = 5 pF |
400 | ps | ||
TF | Output fall time | 80% to 20%, RL = 50 Ω, CL = 5 pF |
400 | ps | ||
DIGITAL OUTPUTS (Status_CLKinX, Status_LD, Status_Holdover, SYNC) | ||||||
VOH | High-level output voltage | IOH = -500 µA | VCC – 0.4 | V | ||
VOL | Low-level output voltage | IOL = 500 µA | 0.4 | V | ||
DIGITAL INPUTS (Status_CLKinX, SYNC) | ||||||
VIH | High-level input voltage | 1.6 | VCC | V | ||
VIL | Low-level input voltage | 0.4 | V | |||
IIH | High-level input current VIH = VCC |
Status_CLKinX_TYPE = 0 (High Impedance) |
–5 | 5 | µA | |
Status_CLKinX_TYPE = 1 (Pull-up) |
–5 | 5 | ||||
Status_CLKinX_TYPE = 2 (Pull-down) |
10 | 80 | ||||
IIL | Low-level input current VIL = 0 V |
Status_CLKinX_TYPE = 0 (High Impedance) |
–5 | 5 | µA | |
Status_CLKinX_TYPE = 1 (Pull-up) |
–40 | -5 | ||||
Status_CLKinX_TYPE = 2 (Pull-down) |
–5 | 5 | ||||
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire) | ||||||
VIH | High-level input voltage | 1.6 | VCC | V | ||
VIL | Low-level input voltage | 0.4 | V | |||
IIH | High-level input current | VIH = VCC | 5 | 25 | µA | |
IIL | Low-level input current | VIL = 0 | –5 | 5 | µA |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
TECS | LE to clock set up time | See Figure 1 through Figure 4 | 25 | ns | ||
TDCS | Data to clock set up time | See Figure 1 | 25 | ns | ||
TCDH | Clock to data hold time | See Figure 1 | 8 | ns | ||
TCWH | Clock pulse width high | See Figure 1, Figure 2, and Figure 4 | 25 | ns | ||
TCWL | Clock pulse width low | See Figure 1, Figure 2, and Figure 4 | 25 | ns | ||
TCES | Clock to LE set up time | See Figure 1 through Figure 4 | 25 | ns | ||
TEWH | LE pulse width | See Figure 1, Figure 2, and Figure 4 | 25 | ns | ||
TCR | Falling clock to readback time | See Figure 4 | 25 | ns |