JAJSDF8B March   2017  – July 2019 LMK04616

PRODUCTION DATA.  

  1. 1特長
  2. 2アプリケーション
  3. 3概要
    1.     概略回路図
  4. 4改訂履歴
  5. 5概要 (続き)
    1. 5.1 Device Comparison Table
    2. 5.2 Pin Configuration and Functions
      1.      Pin Functions: LMK04616
    3. 5.3 Specifications
      1. 5.3.1  Absolute Maximum Ratings
      2. 5.3.2  ESD Ratings
      3. 5.3.3  Recommended Operating Conditions
      4. 5.3.4  Thermal Information
      5. 5.3.5  Digital Input and Output Characteristics (CLKin_SEL, STATUSx, SYNC, RESETN)
      6. 5.3.6  Clock Input Characteristics (CLKinX)
      7. 5.3.7  Clock Input Characteristics (OSCin)
      8. 5.3.8  PLL1 Specification Characteristics
      9. 5.3.9  PLL2 Specification Characteristics
      10. 5.3.10 Clock Output Type Characteristics (CLKoutX)
      11. 5.3.11 Oscillator Output Characteristics (OSCout)
      12. 5.3.12 Jitter and Phase Noise Characteristics for CLKoutX and OSCout
      13. 5.3.13 Clock Output Skew and Isolation Characteristics
      14. 5.3.14 Clock Output Delay Characteristics
      15. 5.3.15 DEFAULT POWER on RESET CLOCK OUTPUT Characteristics
      16. 5.3.16 Power Supply Characteristics
      17. 5.3.17 Typical Power Supply Noise Rejection Characteristics
      18. 5.3.18 SPI Interface Timing
      19. 5.3.19 Timing Diagram
      20. 5.3.20 Typical Characteristics
        1. 5.3.20.1 Clock Output AC Characteristics
    4. 5.4 Parameter Measurement Information
      1. 5.4.1 Differential Voltage Measurement Terminology
      2. 5.4.2 Output Termination Scheme
        1. 5.4.2.1 HSDS 4/6/8mA
        2. 5.4.2.2 HCSL
        3. 5.4.2.3 LVCMOS
    5. 5.5 Detailed Description
      1. 5.5.1 Overview
        1. 5.5.1.1 Jitter Cleaning
        2. 5.5.1.2 Four Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, CLKin2/CLKin2*, and CLKin3/CLKin3*)
        3. 5.5.1.3 VCXO Buffered Output
        4. 5.5.1.4 Frequency Holdover
        5. 5.5.1.5 Integrated Programmable PLL1 and PLL2 Loop Filter
        6. 5.5.1.6 Internal VCOs
        7. 5.5.1.7 Clock Distribution
          1. 5.5.1.7.1 Output Clock Divider
          2. 5.5.1.7.2 Output Clock Delay
          3. 5.5.1.7.3 Glitchless Half-Step and Glitchless Analog Delay
          4. 5.5.1.7.4 Programmable Output Formats
          5. 5.5.1.7.5 Clock Output SYNChronization
        8. 5.5.1.8 Status Pins
      2. 5.5.2 Functional Block Diagram
      3. 5.5.3 Feature Description
        1. 5.5.3.1 Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, CLKin2/CLKin2*, and CLKin3/CLKin3*)
          1. 5.5.3.1.1 Input Clock Switching
            1. 5.5.3.1.1.1 Input Clock Switching – Register Select Mode
            2. 5.5.3.1.1.2 Input Clock Switching – Pin Select Mode (CLKin_SEL, STATUS0)
              1. 5.5.3.1.1.2.1 Configuring Pin Select Mode
            3. 5.5.3.1.1.3 Input Clock Switching – Automatic Mode
          2. 5.5.3.1.2 Loss of Signal Detection – LOS
            1. 5.5.3.1.2.1 LOS – Assertion
            2. 5.5.3.1.2.2 LOS – Reference Clock Recovery
          3. 5.5.3.1.3 Driving CLKin and OSCin Inputs
            1. 5.5.3.1.3.1 Driving CLKin and OSCin Pins With a Differential Source
            2. 5.5.3.1.3.2 Driving CLKin and OSCin Pins With a Single-Ended Source
        2. 5.5.3.2 Clock Outputs (CLKoutX)
          1. 5.5.3.2.1 HCSL
          2. 5.5.3.2.2 HSDS
          3. 5.5.3.2.3 SYNC
          4. 5.5.3.2.4 Digital Delay
            1. 5.5.3.2.4.1 Fixed Digital Delay
            2. 5.5.3.2.4.2 Dynamic Digital Delay
          5. 5.5.3.2.5 Analog Delay
        3. 5.5.3.3 OSCout
          1. 5.5.3.3.1 Pin-Controlled OSCout Divider
        4. 5.5.3.4 STATUS0/1 and SYNC Pin Functions
          1. 5.5.3.4.1 Common STATUS0/1 and SYNC Pin Functions
          2. 5.5.3.4.2 Additional STATUS0 Pin Functions
          3. 5.5.3.4.3 Additional SYNC Pin Functions
        5. 5.5.3.5 PLL1 and PLL2
          1. 5.5.3.5.1 PLL1
            1. 5.5.3.5.1.1 PLL1 Proportional Modes
            2. 5.5.3.5.1.2 PLL1 Higher Order Poles
          2. 5.5.3.5.2 PLL2
            1. 5.5.3.5.2.1 PLL2 Divider
            2. 5.5.3.5.2.2 PLL2 Input Modes
            3. 5.5.3.5.2.3 PLL2 Loop Filter
            4. 5.5.3.5.2.4 PLL2 3rd Order Loop Filter
            5. 5.5.3.5.2.5 PLL2 Voltage Controlled Oscillator (VCO)
            6. 5.5.3.5.2.6 Examples of PLL2 Setting
          3. 5.5.3.5.3 Digital Lock Detect
            1. 5.5.3.5.3.1 Calculating Digital Lock Detect Frequency Accuracy
        6. 5.5.3.6 Holdover
          1. 5.5.3.6.1 Holdover Flowchart
          2. 5.5.3.6.2 Enable Holdover
            1. 5.5.3.6.2.1 Automatic Tracked CTRL_VCXO Holdover Mode
          3. 5.5.3.6.3 Enter Holdover
            1. 5.5.3.6.3.1 LOS_x Detect
            2. 5.5.3.6.3.2 PLL1 DLD Detect
            3. 5.5.3.6.3.3 CTRL_VCXO Rail Detect
              1. 5.5.3.6.3.3.1 Absolute Limits
              2. 5.5.3.6.3.3.2 Relative Limits
            4. 5.5.3.6.3.4 Manual Holdover Enable – Register Control
            5. 5.5.3.6.3.5 Manual Holdover Enable – Pin Control
            6. 5.5.3.6.3.6 Start-Up into Holdover
          4. 5.5.3.6.4 During Holdover
          5. 5.5.3.6.5 Exiting Holdover
          6. 5.5.3.6.6 Holdover Frequency Accuracy
          7. 5.5.3.6.7 Holdover Mode – Automatic Exit by LOS Deassertion
          8. 5.5.3.6.8 Holdover Mode – Automatic Exit of Holdover With Holdover Counter
        7. 5.5.3.7 JEDEC JESD204B
          1. 5.5.3.7.1 SYNC Pins
          2. 5.5.3.7.2 SYNC modes
          3. 5.5.3.7.3 SYSREF Modes
            1. 5.5.3.7.3.1 SYSREF Pulser
              1. 5.5.3.7.3.1.1 SPI Pulser Mode
              2. 5.5.3.7.3.1.2 Pin Pulser Mode
              3. 5.5.3.7.3.1.3 Multiple SYSREF Frequencies
            2. 5.5.3.7.3.2 Continuous SYSREF
            3. 5.5.3.7.3.3 SYSREF Request
          4. 5.5.3.7.4 How to Enable SYSREF
            1. 5.5.3.7.4.1 Setup Example 1: Pulser Mode, Pin Controlled
            2. 5.5.3.7.4.2 Setup Example 2: Pulser Mode, Spi Controlled
        8. 5.5.3.8 Zero Delay Mode (ZDM)
        9. 5.5.3.9 Power-Up Sequence
      4. 5.5.4 Device Functional Modes
        1. 5.5.4.1 Dual PLL
        2. 5.5.4.2 Single PLL
        3. 5.5.4.3 PLL2 Bypass
        4. 5.5.4.4 Clock Distribution
      5. 5.5.5 Programming
        1. 5.5.5.1 Recommended Programming Sequence
          1. 5.5.5.1.1 Readback
      6. 5.5.6 Register Maps
        1. 5.5.6.1 Register Map for Device Programming
        2. 5.5.6.2 Device Register Descriptions
          1. 5.5.6.2.1   CONFIGA
          2. 5.5.6.2.2   RESERVED1
          3. 5.5.6.2.3   RESERVED2
          4. 5.5.6.2.4   CHIP_TYPE
          5. 5.5.6.2.5   CHIP_ID_BY1
          6. 5.5.6.2.6   CHIP_ID_BY0
          7. 5.5.6.2.7   CHIP_VER
          8. 5.5.6.2.8   RESERVED3
          9. 5.5.6.2.9   RESERVED4
          10. 5.5.6.2.10  RESERVED5
          11. 5.5.6.2.11  RESERVED6
          12. 5.5.6.2.12  RESERVED7
          13. 5.5.6.2.13  VENDOR_ID_BY1
          14. 5.5.6.2.14  VENDOR_ID_BY0
          15. 5.5.6.2.15  RESERVED8
          16. 5.5.6.2.16  RESERVED9
          17. 5.5.6.2.17  STARTUP_CFG
          18. 5.5.6.2.18  STARTUP
          19. 5.5.6.2.19  DIGCLKCTRL
          20. 5.5.6.2.20  PLL2REFCLKDIV
          21. 5.5.6.2.21  GLBL_SYNC_SYSREF
          22. 5.5.6.2.22  CLKIN_CTRL0
          23. 5.5.6.2.23  CLKIN_CTRL1
          24. 5.5.6.2.24  CLKIN0CTRL
          25. 5.5.6.2.25  CLKIN1CTRL
          26. 5.5.6.2.26  CLKIN2CTRL
          27. 5.5.6.2.27  CLKIN3CTRL
          28. 5.5.6.2.28  CLKIN0RDIV_BY1
          29. 5.5.6.2.29  CLKIN0RDIV_BY0
          30. 5.5.6.2.30  CLKIN1RDIV_BY1
          31. 5.5.6.2.31  CLKIN1RDIV_BY0
          32. 5.5.6.2.32  CLKIN2RDIV_BY1
          33. 5.5.6.2.33  CLKIN2RDIV_BY0
          34. 5.5.6.2.34  CLKIN3RDIV_BY1
          35. 5.5.6.2.35  CLKIN3RDIV_BY0
          36. 5.5.6.2.36  CLKIN0LOS_REC_CNT
          37. 5.5.6.2.37  CLKIN0LOS_LAT_SEL
          38. 5.5.6.2.38  CLKIN1LOS_REC_CNT
          39. 5.5.6.2.39  CLKIN1LOS_LAT_SEL
          40. 5.5.6.2.40  CLKIN2LOS_REC_CNT
          41. 5.5.6.2.41  CLKIN2LOS_LAT_SEL
          42. 5.5.6.2.42  CLKIN3LOS_REC_CNT
          43. 5.5.6.2.43  CLKIN3LOS_LAT_SEL
          44. 5.5.6.2.44  CLKIN_SWCTRL0
          45. 5.5.6.2.45  CLKIN_SWCTRL1
          46. 5.5.6.2.46  CLKIN_SWCTRL2
          47. 5.5.6.2.47  OSCIN_CTRL
          48. 5.5.6.2.48  OSCOUT_CTRL
          49. 5.5.6.2.49  OSCOUT_DIV
          50. 5.5.6.2.50  OSCOUT_DRV
          51. 5.5.6.2.51  OUTCH_SWRST
          52. 5.5.6.2.52  OUTCH01CNTL0
          53. 5.5.6.2.53  OUTCH01CNTL1
          54. 5.5.6.2.54  OUTCH23CNTL0
          55. 5.5.6.2.55  OUTCH23CNTL1
          56. 5.5.6.2.56  OUTCH45CNTL0
          57. 5.5.6.2.57  OUTCH45CNTL1
          58. 5.5.6.2.58  OUTCH67CNTL0
          59. 5.5.6.2.59  OUTCH67CNTL1
          60. 5.5.6.2.60  OUTCH89CNTL0
          61. 5.5.6.2.61  OUTCH89CNTL1
          62. 5.5.6.2.62  OUTCH1011CNTL0
          63. 5.5.6.2.63  OUTCH1011CNTL1
          64. 5.5.6.2.64  OUTCH1213CNTL0
          65. 5.5.6.2.65  OUTCH1213CNTL1
          66. 5.5.6.2.66  OUTCH1415CNTL0
          67. 5.5.6.2.67  OUTCH1415CNTL1
          68. 5.5.6.2.68  OUTCH01DIV_BY1
          69. 5.5.6.2.69  OUTCH01DIV_BY0
          70. 5.5.6.2.70  OUTCH23DIV_BY1
          71. 5.5.6.2.71  OUTCH23DIV_BY0
          72. 5.5.6.2.72  OUTCH45DIV_BY1
          73. 5.5.6.2.73  OUTCH45DIV_BY0
          74. 5.5.6.2.74  OUTCH67DIV_BY1
          75. 5.5.6.2.75  OUTCH67DIV_BY0
          76. 5.5.6.2.76  OUTCH89DIV_BY1
          77. 5.5.6.2.77  OUTCH89DIV_BY0
          78. 5.5.6.2.78  OUTCH1011DIV_BY1
          79. 5.5.6.2.79  OUTCH1011DIV_BY0
          80. 5.5.6.2.80  OUTCH1213DIV_BY1
          81. 5.5.6.2.81  OUTCH1213DIV_BY0
          82. 5.5.6.2.82  OUTCH1415DIV_BY1
          83. 5.5.6.2.83  OUTCH1415DIV_BY0
          84. 5.5.6.2.84  OUTCH_DIV_INV
          85. 5.5.6.2.85  PLL1CTRL0
          86. 5.5.6.2.86  PLL1CTRL1
          87. 5.5.6.2.87  PLL1CTRL2
          88. 5.5.6.2.88  PLL1_SWRST
          89. 5.5.6.2.89  PLL1WNDWSIZE
          90. 5.5.6.2.90  PLL1STRCELL
          91. 5.5.6.2.91  PLL1CPSETTING
          92. 5.5.6.2.92  PLL1CPSETTING_FL
          93. 5.5.6.2.93  PLL1_HOLDOVER_CTRL1
          94. 5.5.6.2.94  PLL1_HOLDOVER_MAXCNT_BY3
          95. 5.5.6.2.95  PLL1_HOLDOVER_MAXCNT_BY2
          96. 5.5.6.2.96  PLL1_HOLDOVER_MAXCNT_BY1
          97. 5.5.6.2.97  PLL1_HOLDOVER_MAXCNT_BY0
          98. 5.5.6.2.98  PLL1_NDIV_BY1
          99. 5.5.6.2.99  PLL1_NDIV_BY0
          100. 5.5.6.2.100 PLL1_LOCKDET_CYC_CNT_BY2
          101. 5.5.6.2.101 PLL1_LOCKDET_CYC_CNT_BY1
          102. 5.5.6.2.102 PLL1_LOCKDET_CYC_CNT_BY0
          103. 5.5.6.2.103 RSRVD_0x66
          104. 5.5.6.2.104 RSRVD_0x67
          105. 5.5.6.2.105 RSRVD_0x68
          106. 5.5.6.2.106 RSRVD_0x69
          107. 5.5.6.2.107 PLL1_STRG
          108. 5.5.6.2.108 PLL1RCCLKDIV
          109. 5.5.6.2.109 PLL2_CTRL0
          110. 5.5.6.2.110 PLL2_CTRL1
          111. 5.5.6.2.111 PLL2_CTRL2
          112. 5.5.6.2.112 PLL2_SWRST
          113. 5.5.6.2.113 PLL2_LF_C4R4
          114. 5.5.6.2.114 PLL2_LF_C3R3
          115. 5.5.6.2.115 PLL2_CP_SETTING
          116. 5.5.6.2.116 PLL2_NDIV_BY1
          117. 5.5.6.2.117 PLL2_NDIV_BY0
          118. 5.5.6.2.118 PLL2_RDIV_BY1
          119. 5.5.6.2.119 PLL2_RDIV_BY0
          120. 5.5.6.2.120 PLL2_STRG_INIT_BY1
          121. 5.5.6.2.121 PLL2_STRG_INIT_BY0
          122. 5.5.6.2.122 RAILDET_UP
          123. 5.5.6.2.123 RAILDET_LOW
          124. 5.5.6.2.124 PLL2_AC_CTRL
          125. 5.5.6.2.125 PLL2_CURR_STOR_CELL
          126. 5.5.6.2.126 PLL2_AC_THRESHOLD
          127. 5.5.6.2.127 PLL2_AC_STRT_THRESHOLD
          128. 5.5.6.2.128 PLL2_AC_WAIT_CTRL
          129. 5.5.6.2.129 PLL2_AC_JUMPSTEP
          130. 5.5.6.2.130 PLL2_LD_WNDW_SIZE
          131. 5.5.6.2.131 PLL2_LD_WNDW_SIZE_INITIAL
          132. 5.5.6.2.132 PLL2_LOCKDET_CYC_CNT_BY2
          133. 5.5.6.2.133 PLL2_LOCKDET_CYC_CNT_BY1
          134. 5.5.6.2.134 PLL2_LOCKDET_CYC_CNT_BY0
          135. 5.5.6.2.135 PLL2_LOCKDET_CYC_CNT_INITIAL_BY2
          136. 5.5.6.2.136 PLL2_LOCKDET_CYC_CNT_INITIAL_BY1
          137. 5.5.6.2.137 PLL2_LOCKDET_CYC_CNT_INITIAL_BY0
          138. 5.5.6.2.138 IOCTRL_SPI0
          139. 5.5.6.2.139 IOCTRL_SPI1
          140. 5.5.6.2.140 IOTEST_SDIO
          141. 5.5.6.2.141 IOTEST_SCL
          142. 5.5.6.2.142 IOTEST_SCS
          143. 5.5.6.2.143 IOCTRL_STAT0
          144. 5.5.6.2.144 IOCTRL_STAT1
          145. 5.5.6.2.145 STAT1MUX
          146. 5.5.6.2.146 STAT0MUX
          147. 5.5.6.2.147 STATPLL2CLKDIV
          148. 5.5.6.2.148 IOTEST_STAT0
          149. 5.5.6.2.149 IOTEST_STAT1
          150. 5.5.6.2.150 IOCTRL_SYNC
          151. 5.5.6.2.151 DUMMY_REGISTER_1
          152. 5.5.6.2.152 IOCTRL_CLKINSEL1
          153. 5.5.6.2.153 IOTEST_CLKINSEL1
          154. 5.5.6.2.154 PLL1_TSTMODE
          155. 5.5.6.2.155 PLL2_CTRL
          156. 5.5.6.2.156 PLL2_RDIV_CLKEN
          157. 5.5.6.2.157 PLL2_NDIV_CLKEN
          158. 5.5.6.2.158 STATUS
          159. 5.5.6.2.159 PLL2_DLD_EN
          160. 5.5.6.2.160 PLL2_DUAL_LOOP
          161. 5.5.6.2.161 CH01_DDLY_BY0
          162. 5.5.6.2.162 CH23_DDLY_BY0
          163. 5.5.6.2.163 CH45_DDLY_BY0
          164. 5.5.6.2.164 CH67_DDLY_BY0
          165. 5.5.6.2.165 CH89_DDLY_BY0
          166. 5.5.6.2.166 CH1011_DDLY_BY0
          167. 5.5.6.2.167 CH1213_DDLY_BY0
          168. 5.5.6.2.168 CH1415_DDLY_BY0
          169. 5.5.6.2.169 OUTCH0_JESD_CTRL
          170. 5.5.6.2.170 OUTCH1_JESD_CTRL
          171. 5.5.6.2.171 OUTCH2_JESD_CTRL
          172. 5.5.6.2.172 OUTCH3_JESD_CTRL
          173. 5.5.6.2.173 OUTCH4_JESD_CTRL
          174. 5.5.6.2.174 OUTCH5_JESD_CTRL
          175. 5.5.6.2.175 OUTCH6_JESD_CTRL
          176. 5.5.6.2.176 OUTCH7_JESD_CTRL
          177. 5.5.6.2.177 OUTCH8_JESD_CTRL
          178. 5.5.6.2.178 OUTCH9_JESD_CTRL
          179. 5.5.6.2.179 OUTCH10_JESD_CTRL
          180. 5.5.6.2.180 OUTCH11_JESD_CTRL
          181. 5.5.6.2.181 OUTCH12_JESD_CTRL
          182. 5.5.6.2.182 OUTCH13_JESD_CTRL
          183. 5.5.6.2.183 OUTCH14_JESD_CTRL
          184. 5.5.6.2.184 OUTCH15_JESD_CTRL
          185. 5.5.6.2.185 CLKMUXVECTOR
          186. 5.5.6.2.186 OUTCH01CNTL2
          187. 5.5.6.2.187 OUTCH23CNTL2
          188. 5.5.6.2.188 OUTCH45CNTL2
          189. 5.5.6.2.189 OUTCH67CNTL2
          190. 5.5.6.2.190 OUTCH89CNTL2
          191. 5.5.6.2.191 OUTCH1011CNTL2
          192. 5.5.6.2.192 OUTCH1213CNTL2
          193. 5.5.6.2.193 OUTCH1415CNTL2
          194. 5.5.6.2.194 OUTCH0_JESD_CTRL1
          195. 5.5.6.2.195 OUTCH1_JESD_CTRL1
          196. 5.5.6.2.196 OUTCH2_JESD_CTRL1
          197. 5.5.6.2.197 OUTCH3_JESD_CTRL1
          198. 5.5.6.2.198 OUTCH4_JESD_CTRL1
          199. 5.5.6.2.199 OUTCH5_JESD_CTRL1
          200. 5.5.6.2.200 OUTCH6_JESD_CTRL1
          201. 5.5.6.2.201 OUTCH7_JESD_CTRL1
          202. 5.5.6.2.202 OUTCH8_JESD_CTRL1
          203. 5.5.6.2.203 OUTCH9_JESD_CTRL1
          204. 5.5.6.2.204 OUTCH10_JESD_CTRL1
          205. 5.5.6.2.205 OUTCH11_JESD_CTRL1
          206. 5.5.6.2.206 OUTCH12_JESD_CTRL1
          207. 5.5.6.2.207 OUTCH13_JESD_CTRL1
          208. 5.5.6.2.208 OUTCH14_JESD_CTRL1
          209. 5.5.6.2.209 OUTCH15_JESD_CTRL1
          210. 5.5.6.2.210 SYSREF_PLS_CNT
          211. 5.5.6.2.211 SYNCMUX
          212. 5.5.6.2.212 IOTEST_SYNC
          213. 5.5.6.2.213 OUTCH_ZDM
          214. 5.5.6.2.214 PLL2_CTRL3
          215. 5.5.6.2.215 PLL1_HOLDOVER_CTRL0
          216. 5.5.6.2.216 IOCTRL_SYNC_1
          217. 5.5.6.2.217 OUTCH_TOP_JESD_CTRL
          218. 5.5.6.2.218 OUTCH_BOT_JESD_CTRL
          219. 5.5.6.2.219 OUTCH_JESD_CTRL1
          220. 5.5.6.2.220 PLL2_CTRL4
          221. 5.5.6.2.221 PLL2_CTRL5
          222. 5.5.6.2.222 PLL2_CTRL6
          223. 5.5.6.2.223 PLL2_CTRL7
    6. 5.6 Application and Implementation
      1. 5.6.1 Application Information
        1. 5.6.1.1 Digital Lock Detect Frequency Accuracy
          1. 5.6.1.1.1 Minimum Lock Time Calculation Example
      2. 5.6.2 Typical Application
        1. 5.6.2.1 Design Requirements
        2. 5.6.2.2 Detailed Design Procedure
          1. 5.6.2.2.1 PLL Loop Filter Design
          2. 5.6.2.2.2 Clock Output Assignment
          3. 5.6.2.2.3 Calculation Using LCM
          4. 5.6.2.2.4 Device Programming
          5. 5.6.2.2.5 Device Selection
          6. 5.6.2.2.6 Clock Architect
        3. 5.6.2.3 Application Curves
      3. 5.6.3 Do's and Don'ts
        1. 5.6.3.1 Pin Connection Recommendations
    7. 5.7 Power Supply Recommendations
      1. 5.7.1 Recommended Power Supply Connection
      2. 5.7.2 Current Consumption / Power Dissipation Calculations
    8. 5.8 Layout
      1. 5.8.1 Layout Guidelines
        1. 5.8.1.1 CLKin and OSCin
        2. 5.8.1.2 CLKout
      2. 5.8.2 Layout Example
  6. 6デバイスおよびドキュメントのサポート
    1. 6.1 デバイス・サポート
      1. 6.1.1 開発サポート
        1. 6.1.1.1 クロック設計ツール
        2. 6.1.1.2 Clock Architect
        3. 6.1.1.3 TICS Pro
    2. 6.2 ドキュメントの更新通知を受け取る方法
    3. 6.3 コミュニティ・リソース
    4. 6.4 商標
    5. 6.5 静電気放電に関する注意事項
    6. 6.6 Glossary
  7. 7メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
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5.5.3.5.1 PLL1

PLL1 in LMK0461x is a very low bandwidth PLL. The PLL is a fully programmable, ultra-flexible design and is intended to be used for jitter cleaning of the noisy input clock. The PLL uses a semi-digital architecture and there is no need for external loop filter. The loop-filter has separated integral and proportional paths, which can be programmed individually to define the PLL transfer. There is a possibility to add higher order poles by connecting a capacitor outside the chip with a fixed on-chip resistor RCTRL. The block diagram of the PLL1 is shown in Figure 36. The PLL uses an external VCXO as a voltage controlled oscillator. Both positive and negative gain VCXOs are supported by LMK046xx.

LMK04616 PLL1_p_LMK04610.gifFigure 36. PLL1 Block Diagram

To reduce lock time, PLL1 supports two locking modes which can be individually configured by the user. When configured, PLL1 starts with Fastlock (with very high integral gain) and after lock, it switches to desired integral gain.

PLL1 Bandwidth depends on the VCXO gain and loop parameters. LMK0461x PLLs are designed with active damping technique. For a given VCXO gain and divider settings, the bandwidth can be programmed by using the PLL1_PROP settings. The higher the value, the higher the bandwidth.

Table 13 shows the internal PLL1 parameter, register and programming ranges. Use the TICS Pro EVM tool to calculate PLL1_PROP, PLL1_PROP_LF, PLL1_INTG, and PLL1_INTG_LF values.

Table 13. PLL1 Parameter and Register

PARAMETER REGISTER DESCRIPTION MIN TYP MAX UNIT
CLKINx_PLL1_RDIV 0x1B,0x1C,0X1D,0x1E, 0x1F,0x20,0x21,0x22 Input clock divider for PLL1 1 32771
PLL1_NDIV 0x61,0x62 Feedback clock divider for PLL1 1 32771
PLL1_PROP 0x5A Proportional gain setting 0 127
PLL1_PROP_FL 0x5B Proportional gain setting for Fast Lock 0 127
PLL1_INTG 0x59 Integral gain setting, C3 = 2.2 µF
1.92 MHz PDF, PLL1_PROP < 7		 0 0 1
PLL1_INTG_FL 0x59 Integral gain setting for Fast lock, C3 = 2.2 µF
1.92 MHz PDF, PLL1_PROP < 7		 0 1 1
PLL1_INTG 0x59 Integral gain setting, C3 = 2.2 µF
1.92 MHz PDF, PLL1_PROP ≥ 7		 0 0 3
PLL1_INTG_FL 0x59 Integral gain setting for Fast lock, C3 = 2.2 µF
1.92 MHz PDF, PLL1_PROP ≥ 7		 0 3 3
PLL1_INTG 0x59 Integral gain setting, C3 = 2.2 µF
0.12 MHz PDF, PLL1_PROP < 31		 0 0 2
PLL1_INTG_FL 0x59 Integral gain setting for Fast lock, C3 = 2.2 µF
0.12 MHz PDF, PLL1_PROP < 31		 0 2 2
PLL1_INTG 0x59 Integral gain setting, C3 = 2.2 µF
0.12 MHz PDF, PLL1_PROP ≥ 31		 0 0 15
PLL1_INTG_FL 0x59 Integral gain setting for Fast lock, C3 = 2.2 µF
0.12 MHz PDF, PLL1_PROP ≥ 31		 0 15 15
RCTRL 500 Ω