The LMK04816 device is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual-loop PLLATINUM architecture enables 111-fs RMS jitter (12 kHz to
20 MHz) using a low-noise VCXO module or sub-200-fs RMS jitter (12 kHz to 20 MHz) using a low-cost external crystal and varactor diode.
The dual-loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMK04816 | WQFN (64) | 9.00 mm × 9.00 mm |
Changes from B Revision (April 2013) to C Revision
Changes from A Revision (April 2013) to B Revision
PIN | I/O | TYPE | DESCRIPTION | |
---|---|---|---|---|
NO. | NAME | |||
1, 2 | CLKout0, CLKout0* | O | Programmable | Clock output 0 (clock group 0) |
3, 4 | CLKout1*, CLKout1 | O | Programmable | Clock output 1 (clock group 0) |
6 | SYNC | I/O | Programmable | CLKout Synchronization input or programmable status pin |
Status_CLKin2 | I/O | Input for pin control of PLL1 reference clock selection. CLKin2 LOS status and other options available by programming. | ||
5, 7, 8, 9 | NC | — | — | No Connection. These pins must be left floating. |
10 | Vcc1 | — | PWR | Power supply for VCO LDO |
11 | LDObyp1 | — | ANLG | LDO Bypass, bypassed to ground with 10-µF capacitor |
12 | LDObyp2 | — | ANLG | LDO Bypass, bypassed to ground with a 0.1-µF capacitor |
13, 14 | CLKout2, CLKout2* | O | Programmable | Clock output 2 (clock group 1) |
15, 16 | CLKout3*, CLKout3 | O | Programmable | Clock output 3 (clock group 1) |
17 | Vcc2 | — | PWR | Power supply for clock group 1: CLKout2 and CLKout3 |
18 | Vcc3 | — | PWR | Power supply for clock group 2: CLKout4 and CLKout5 |
19, 20 | CLKout4, CLKout4* | O | Programmable | Clock output 4 (clock group 2) |
21, 22 | CLKout5*, CLKout5 | O | Programmable | Clock output 5 (clock group 2) |
23 | GND | — | PWR | Ground |
24 | Vcc4 | — | PWR | Power supply for digital |
25, 26 | CLKin1, CLKin1* | I | ANLG | Reference Clock Input Port 1 for PLL1. AC- or DC-Coupled |
FBCLKin, FBCLKin* | Feedback input for external clock feedback input (0-delay mode). AC- or DC-Coupled | |||
Fin, Fin* | External VCO input (External VCO mode). AC- or DC-Coupled | |||
27 | Status_Holdover | I/O | Programmable | Programmable status pin, default readback output. Programmable to holdover mode indicator. Other options available by programming. |
28, 29 | CLKin0, CLKin0* | I | ANLG | Reference Clock Input Port 0 for PLL1, AC- or DC-Coupled |
30 | Vcc5 | — | PWR | Power supply for clock inputs |
31, 32 | CLKin2, CLKin2* | I | ANLG | Reference Clock Input Port 2 for PLL1, AC- or DC-Coupled |
33 | Status_LD | I/O | Programmable | Programmable status pin, default lock detect for PLL1 and PLL2. Other options available by programming. |
34 | CPout1 | O | ANLG | Charge pump 1 output |
35 | Vcc6 | — | PWR | Power supply for PLL1, charge pump 1 |
36, 37 | OSCin, OSCin* | I | ANLG | Feedback to PLL1, Reference input to PLL2, AC-Coupled |
38 | Vcc7 | — | PWR | Power supply for OSCin port |
39, 40 | OSCout0, OSCout0* | O | Programmable | Buffered output 0 of OSCin port |
41 | Vcc8 | — | PWR | Power supply for PLL2, charge pump 2 |
42 | CPout2 | O | ANLG | Charge pump 2 output |
43 | Vcc9 | — | PWR | Power supply for PLL2 |
44 | LEuWire | I | CMOS | MICROWIRE Latch Enable Input |
45 | CLKuWire | I | CMOS | MICROWIRE Clock Input |
46 | DATAuWire | I | CMOS | MICROWIRE Data Input |
47 | Vcc10 | — | PWR | Power supply for clock group 3: CLKout6 and CLKout7 |
48, 49 | CLKout6, CLKout6* | O | Programmable | Clock output 6 (clock group 3) |
50, 51 | CLKout7*, CLKout7 | O | Programmable | Clock output 7 (clock group 3) |
52 | Vcc11 | — | PWR | Power supply for clock group 4: CLKout8 and CLKout9 |
53, 54 | CLKout8, CLKout8* | O | Programmable | Clock output 8 (clock group 4) |
55, 56 | CLKout9*, CLKout9 | O | Programmable | Clock output 9 (clock group 4) |
57 | Vcc12 | — | PWR | Power supply for clock group 5: CLKout10 and CLKout11 |
58, 59 | CLKout10, CLKout10* | O | Programmable | Clock output 10 (clock group 5) |
60, 61 | CLKout11*, CLKout11 | O | Programmable | Clock output 11 (clock group 5) |
62 | Status_CLKin0 | I/O | Programmable | Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin0 LOS status and other options available by programming. |
63 | Status_CLKin1 | I/O | Programmable | Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin1 LOS status and other options available by programming. |
64 | Vcc13 | — | PWR | Power supply for clock group 0: CLKout0 and CLKout1 |
DAP | DAP | — | GND | DIE ATTACH PAD, connect to GND |