SNAS605AS March 2013 – May 2020 LMK04821 , LMK04826 , LMK04828
PRODUCTION DATA.
The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A window size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback signals of the PLL, for each event to occur. When a PLL digital lock event occurs, the PLL digital lock detect is asserted true. When the holdover exit event occurs, the device exits holdover mode.
EVENT | PLL | WINDOW SIZE | LOCK COUNT |
---|---|---|---|
PLL1 locked | PLL1 | PLL1_WND_SIZE | PLL1_DLD_CNT |
PLL2 locked | PLL2 | PLL2_WND_SIZE | PLL2_DLD_CNT |
Holdover exit | PLL1 | PLL1_WND_SIZE | HOLDOVER_DLD_CNT |
For a digital lock detect event to occur, there must be a “lock count” number of phase-detector cycles of PLLX, during which the time/phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the user programmable "window size." Because there must be at least "lock count" phase-detector events before a lock event occurs, a minimum digital lock event time can be calculated as "lock count" / fPDX, where X = 1 for PLL1 or 2 for PLL2.
By using Equation 6, values for a "lock count" and "window size" can be chosen to set the frequency accuracy required by the system in ppm before the digital lock detect event occurs:
The effect of the "lock count" value is that it shortens the effective lock window size by dividing the "window size" by "lock count".
If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by "window size", then the “lock count” value is reset to 0.