The LMK0482x family is the industry's highest performance clock conditioner with JEDEC JESD204B support.
The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.
The high performance, combined with features such as the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make the LMK0482x family ideal for providing flexible high-performance clocking trees.
PART NUMBER | VCO0 FREQUENCY | VCO1 FREQUENCY |
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LMK04821 | 1930 to 2075 MHz | 2920 to 3080 MHz
VCO1 Div = ÷2 to ÷8 (÷2 = 1460 to 1540 MHz) |
LMK04826 | 1840 to 1970 MHz | 2440 to 2505 MHz |
LMK04828 | 2370 to 2630 MHz | 2920 to 3080 MHz |
Changes from AR Revision (December 2015) to AS Revision
Changes from AQ Revision (August 2014) to AR Revision
Changes from AP Revision (June 2013) to AQ Revision
Changes from AO Revision (March 2013) to AP Revision
PART NUMBER | REF-
ERENCE INPUTS(1) |
OSCout (BUFFERED OSCin Clock) LVDS/ LVPECL/ LVCMOS (1) | PLL2 PROGRAMMABLE LVDS/LVPECL/HSDS OUTPUTS | VCO0 FREQUENCY | VCO1 FREQUENCY |
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LMK04821 | Up to 3 | Up to 1 | 14 | 1930 to 2075 MHz | VCO1_DIV = ÷2
1460 to 1540 MHz |
VCO1_DIV = ÷3
974 to 1026 MHz |
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VCO1_DIV = ÷4
730 to 770 MHz |
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VCO1_DIV = ÷5
584 to 616 MHz |
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VCO1_DIV = ÷6
487 to 513 MHz |
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VCO1_DIV = ÷7
418 to 440 MHz |
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VCO1_DIV = ÷8
365 to 385 MHz |
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LMK04826 | Up to 3 | Up to 1 | 14 | 1840 to 1970 MHz | 2440 to 2505 MHz |
LMK04828 | Up to 3 | Up to 1 | 14 | 2370 to 2630 MHz | 2920 to 3080 MHz |
PIN | I/O(1) | DESCRIPTION(2) | |
---|---|---|---|
NO. | NAME | ||
1 | DCLKout0 | O | Device clock output 0. Differential clock output. Part of clock group 0. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
2 | DCLKout0* | ||
3 | SDCLKout1 | O | SYSREF / Device clock output 1. Differential clock output. Part of clock group 0. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
4 | SDCLKout1* | ||
5 | RESET/GPO | I/O | Device reset input or GPO. If used as a reset input, pin polarity and nominal 160-kΩ pull-up or pull-down are controlled by register settings. If used as an output, can be set to push-pull or open-drain. |
6 | SYNC/SYSREF_REQ | I | Synchronization input.. Can be used to reset dividers, trigger the SYSREF pulser, or request continuous SYSREF from the SYSREF divider. Pin polarity is controlled by register settings. Nominal 160-kΩ pulldown. |
7, | - | NC | Do not connect. These pins must be left floating. |
8 | - | NC | |
9 | - | NC | |
10 | Vcc1_VCO | P | Power supply for VCO LDO. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. |
11 | LDObyp1 | BP | LDO bypass. This pin must be bypassed to ground with 10-µF capacitor placed close to the pin. |
12 | LDObyp2 | BP | LDO bypass.This pin must be bypassed to ground with a 0.1-µF capacitor placed close to the pin. |
13, | SDCLKout3 | O | SYSREF / Device clock output 3. Differential clock output. Part of clock group 1. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
14 | SDCLKout3* | ||
15 | DCLKout2 | O | Device clock output 2. Differential clock output. Part of clock group 1. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
16 | DCLKout2* | ||
17 | Vcc2_CG1 | P | Power supply for clock outputs 2 and 3. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. |
18 | CS* | I | SPI Chip select. Active-low input. Must be pulled up externally or actively driven high when not in use. |
19 | SCK | I | SPI clock. Active-high input. Nominal 160-kΩ pulldown. |
20 | SDIO | I/O | SPI data. This pin can implement bidirectional I/O. As an output, this pin can be configured for open-drain or push-pull. Open-drain output requires external pull-up. Register settings can disable the output feature of this pin. Other GPIO pins can also be configured as SPI MISO (master-in slave-out) for traditional 4-wire SPI. |
21 | Vcc3_SYSREF | P | Power supply for SYSREF divider and SYNC. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. |
22 | SDCLKout5 | O | SYSREF / Device clock output 5. Differential clock output. Part of clock group 2. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
23 | SDCLKout5* | ||
24 | DCLKout4 | O | Device clock output 4. Differential clock output. Part of clock group 2. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
25 | DCLKout4* | ||
26 | Vcc4_CG2 | Power supply for clock outputs 4, 5, 6, and 7. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. | |
27 | DCLKout6 | O | Device clock output 6. Differential clock output. Part of clock group 2. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
28 | DCLKout6* | ||
29 | SDCLKout7 | O | SYSREF / Device clock output 7. Differential clock output. Part of clock group 2. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
30 | SDCLKout7* | ||
31 | Status_LD1 | I/O | Programmable status pin. By default, this pin is configured as an active-high output representing the state of PLL1 lock detect. Other status conditions and output polarity are register-selectable. This pin can be configured for open-drain or push-pull output. |
32 | CPout1 | O | Charge pump 1 output. This pin is connected to the external loop filter components for PLL1, and to the VCXO control voltage pin. |
33 | Vcc5_DIG | P | Power supply for digital circuitry, such as SPI bus and GPIO pins. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. |
34 | CLKin1 | I | (Default) Reference clock input port 1 for PLL1. Can be configured for DC or AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information. |
FBCLKin | I | Feedback input for external clock feedback input (zero–delay mode). Can be configured for DC or AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information. | |
Fin | I | External VCO input (external VCO mode) or Clock Distribution input (distribution mode). Can be configured for DC or AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information. | |
35 | CLKin1* | I | (Default) Reference clock input port 1 for PLL1. Can be configured for DC or AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information. |
FBCLKin* | I | Feedback input for external clock feedback input (zero-delay mode). Can be configured for DC or AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information. | |
Fin* | I | External VCO input (external VCO mode) or Clock Distribution input (distribution mode). Can be configured for DC or AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information. | |
36 | Vcc6_PLL1 | P | Power supply for PLL1, charge pump 1, holdover DAC. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. |
37 | CLKin0 | I | Reference clock input port 0 for PLL1. Can also be used as a synchronization input for SYNC/SYSREF. Can be configured for DC or AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information. |
38 | CLKin0* | ||
39 | Vcc7_OSCout | P | Power supply for OSCout port and CLKin2. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. |
40 | OSCout | I/O | (Default) Buffered output of OSCin port. Defaults to LVPECL. In LVPECL output format, this pin only supports 240-Ω emitter resistors. If unused, set output format buffer to powerdown and leave pins floating. |
CLKin2 | Reference clock input port 2 for PLL1. Can be configured for DC or AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information. Registers must be configured to set this pin as an input. | ||
41 | OSCout* | I/O | (Default) Buffered output of OSCin port. Defaults to LVPECL. In LVPECL output format, this pin only supports 240-Ω emitter resistors. If unused, set output format buffer to powerdown and leave pins floating. |
CLKin2* | Reference clock input port 2 for PLL1. Can be configured for DC or AC coupling. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information. Registers must be configured to set this pin as an input. | ||
42 | Vcc8_OSCin | P | Power supply for OSCin. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. |
43 | OSCin | I | Feedback to PLL1, reference input to PLL2. Inputs to this pin should be AC-coupled. Accepts single-ended or differential clocks. If unused in single-ended configuration, connect to GND with a 0.1-µF capacitor. Leave floating if both pins are unused. See Driving CLKin and OSCin Inputs for single-ended termination information. |
44 | OSCin* | ||
45 | Vcc9_CP2 | P | Power supply for PLL2 charge pump. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. |
46 | CPout2 | O | Charge pump 2 output. This pin is connected to the external components of the PLL2 loop filter. If an external VCO is used, this pin is also connected to the external VCO control voltage pin. Do not route this pin near noisy signals. |
47 | Vcc10_PLL2 | P | Power supply for PLL2. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. |
48 | Status_LD2 | I/O | Programmable status pin. By default, this pin is configured as an active-high output representing the state of PLL2 lock detect. Other status conditions and output polarity are register-selectable. This pin can be configured for open-drain or push-pull output. |
49 | SDCLKout9 | O | SYSREF / Device clock 9. Differential clock output. Part of clock group 3. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
50 | SDCLKout9* | ||
51 | DCLKout8 | O | Device clock output 8. Differential clock output. Part of clock group 3. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
52 | DCLKout8* | ||
53 | Vcc11_CG3 | P | Power supply for clock outputs 8, 9, 10, and 11. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. |
54 | DCLKout10 | O | Device clock output 10. Differential clock output. Part of clock group 3. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
55 | DCLKout10* | ||
56 | SDCLKout11 | O | SYSREF / Device clock output 11. Differential clock output. Part of clock group 3. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
57 | SDCLKout11* | ||
58 | CLKin_SEL0 | I/O | Programmable status pin. By default this pin is programmed as an active-high input with nominal 160-kΩ pulldown that selects which CLKin is used as the reference to PLL1 in pin-select mode. If used as an input, pin polarity and nominal 160-kΩ pull-up or pull-down are controlled by register settings. If used as an output, can be set to push-pull or open-drain. |
59 | CLKin_SEL1 | I/O | Programmable status pin. By default this pin is programmed as an active-high input with nominal 160-kΩ pulldown that selects which CLKin is used as the reference to PLL1 in pin-select mode. If used as an input, pin polarity and nominal 160-kΩ pull-up or pull-down are controlled by register settings. If used as an output, can be set to push-pull or open-drain. |
60 | SDCLKout13 | O | SYSREF / Device clock output 13. Differential clock output. Part of clock group 0. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
61 | SDCLKout13* | ||
62 | DCLKout12 | O | Device clock output 12. Differential clock output. Part of clock group 0. To minimize noise, keep all outputs in the clock group at the same frequency, or at frequencies without spurious interference. If unused, set output format buffer to powerdown and leave pins floating. |
63 | DCLKout12* | ||
64 | Vcc12_CG0 | P | Power supply for clock outputs 0, 1, 12, and 13. Decoupling capacitance requirements may change with system frequency. See Pin Connection Recommendations for recommendations. |
- | DAP | G | Die attach pad. Connect directly to GND plane through multiple vias to minimize resistive and inductive effects and to achieve good thermal performance. All power supply pins are referred to the DAP ground. |