JAJSJN4C May 2020 – November 2022 LMK04832-SP
PRODUCTION DATA
This register controls the feedback feature.
BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|
7 | PLL2_RCLK_MUX | 0 | Selects the source for PLL2 reference. 0: OSCin 1: Currently selected CLKin. | |
6 | NA | 0 | Reserved | |
5 | PLL2_NCLK_MUX | 0 | Selects the input to the PLL2 N Divider 0: PLL2 Prescaler 1: Feedback Mux | |
4:3 | PLL1_NCLK_MUX | 0 | Selects the input to the PLL1 N Divider. 0: OSCin 1: Feedback Mux 2: PLL2 Prescaler | |
2:1 | FB_MUX | 0 | When in 0-delay mode, the feedback mux selects the clock output to be fed back into the PLL1 N Divider. | |
Field Value | Source | |||
0 (0x00) | CLKout6 | |||
1 (0x01) | CLKout8 | |||
2 (0x02) | SYSREF Divider | |||
3 (0x03) | External | |||
0 | FB_MUX_EN | 0 | When using 0-delay, FB_MUX_EN must be set to 1 power up the feedback mux. 0: Feedback mux powered down 1: Feedback mux enabled |