JAJSJN4C May 2020 – November 2022 LMK04832-SP
PRODUCTION DATA
PLL2_N_CAL[17:0]
PLL2 never uses 0-delay during frequency calibration. These registers contain the value of the PLL2 N divider used with PLL2 pre-scaler during calibration for cascaded 0-delay mode. Once calibration is complete, PLL2 will use PLL2_N value. Cascaded 0-delay mode occurs when PLL2_NCLK_MUX = 1.
MSB | — | LSB |
---|---|---|
0x163[1:0] / PLL2_N_CAL[17:16] | 0x164[7:0] / PLL2_N_CAL[15:8] | 0x165[7:0] / PLL2_N_CAL[7:0] |
REGISTER | BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|---|
0x163 | 7:2 | NA | 0 | Reserved | |
0x163 | 1:0 | PLL2_N _CAL[17:16] | 0 | Field Value | Divide Value |
0 (0x00) | Not Valid | ||||
0x164 | 7:0 | PLL2_N_CAL[15:8] | 0 | 1 (0x01) | 1 |
2 (0x02) | 2 | ||||
0x165 | 7:0 | PLL2_N_CAL[7:0] | 12 | ... | ... |
262,143 (0x3FFFF) | 262,143 |