JAJSJN4C May 2020 – November 2022 LMK04832-SP
PRODUCTION DATA
Using the clock design tools configuration the TICS Pro software is manually updated with this information to meet the required application.
Frequency planning for assignment of outputs:
In this example, the 245.76-MHz ADC output needs the best performance. CLKout2 provides the best noise floor / performance. The 245.76 MHz is placed on CLKout2 with 10.24-MHz SYSREF on CLKout3.
In this example, the 983.04-MHz DAC output is placed on CLKout4 and CLKout6 with 10.24-MHz SYSREF on paired CLKout5 and CLKout7 outputs.
In this example, the 122.88-MHz FPGA JESD204B output is placed on CLKout10 with 10.24-MHz SYSREF on paired CLKout11 output.
Additionally, the 122.88-MHz FPGA non-JESD204B outputs are placed on CLKout8 and CLKout9.
Once the device programming is completed as desired in the TICS Pro software, it is possible to export the register settings from the Register tab for use in application.