JAJSJN4C May 2020 – November 2022 LMK04832-SP
PRODUCTION DATA
This register enables dynamic digital delay for enabled device clocks and SYSREF when DDLYd_STEP_CNT is programmed.
BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|
7 | DDLYd _SYSREF_EN | 0 | Enables dynamic digital delay on SYSREF outputs | 0: Disabled 1: Enabled |
6 | DDLYd12_EN | 0 | Enables dynamic digital delay on DCLKout12 | |
5 | DDLYd10_EN | 0 | Enables dynamic digital delay on DCLKout10 | |
4 | DDLYd8_EN | 0 | Enables dynamic digital delay on DCLKout8 | |
3 | DDLYd6_EN | 0 | Enables dynamic digital delay on DCLKout6 | |
2 | DDLYd4_EN | 0 | Enables dynamic digital delay on DCLKout4 | |
1 | DDLYd2_EN | 0 | Enables dynamic digital delay on DCLKout2 | |
0 | DDLYd0_EN | 0 | Enables dynamic digital delay on DCLKout0 |