JAJSJN4C May 2020 – November 2022 LMK04832-SP
PRODUCTION DATA
These registers set the half step for the device clock, the SYSREF output MUX, the SYSREF clock digital delay, and half step.
BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|
7:6 | NA | 0 | Reserved | |
5 | CLKoutY_SRC_MUX | 0 | Select CLKoutX clock source. Source must also be powered up. 0: Device Clock 1: SYSREF | |
4 | SCLKX_Y_PD | 1 | Power down the SYSREF clock output circuitry. 0: SYSREF enabled 1: Power down SYSREF path for clock pair. | |
3:2 | SCLKX_Y_DIS_MODE | 0 | Set disable mode for clock outputs controlled by SYSREF. Some cases will assert when SYSREF_GBL_PD = 1. | |
Field Value | Disable Mode | |||
0 (0x00) | Active in normal operation | |||
1 (0x01) | If SYSREF_GBL_PD = 1, the output is a logic low, otherwise it is active. | |||
2 (0x02) | If SYSREF_GBL_PD = 1, the output is a nominal Vcm voltage for odd clock channels(1) and low for even clocks. Otherwise outputs are active. | |||
3 (0x03) | Output is a nominal Vcm voltage(1) | |||
1 | SCLKX_Y_POL | 0 | Sets the polarity of clock on SCLKX_Y when SYSREF clock output is selected with CLKoutX_MUX or CLKoutY_MUX. 0: Normal 1: Inverted | |
0 | SCLKX_Y_HS | 0 | Sets the local SYSREF clock half step value. 0: No phase adjustment 1: Adjust device SYSREF phase -0.5 clock distribution path cycles. |