JAJSJN4C May 2020 – November 2022 LMK04832-SP
PRODUCTION DATA
Table 8-3 summarizes the bits needed to make SYSREF functionality operational.
REGISTER | FIELD | VALUE | DESCRIPTION |
---|---|---|---|
0x140 | SYSREF_PD | 0 | Must be clear, power-up SYSREF circuitry including the SYSREF divider. |
0x140 | SYSREF_DDLY_PD | 0 | Must be clear to power-up digital delay circuitry. Must be powered up during initial SYNC to ensure deterministic timing to other clock dividers. |
0x143 | SYNC_EN | 1 | Must be set, enable SYNC. |
0x143 | SYSREF_CLR | 1 → 0 | Do not hold local SYSREF DDLY block in reset except at start. Anytime SYSREF_PD = 1 because of user programming or device RESET, it is necessary to set SYSREF_CLR for 15 VCO clock cycles to clear the local SYSREF digital delay. Once cleared, SYSREF_CLR must be cleared to allow SYSREF to operate. |
Enabling JESD204B operation involves synchronizing all the clock dividers with the SYSREF divider, then configuring the actual SYSREF functionality.