JAJSJN4C May 2020 – November 2022 LMK04832-SP
PRODUCTION DATA
Refer to Section 8.3.1.1 for more information on synchronizing PLL1 R divider.
BIT | NAME | POR DEFAULT | DESCRIPTION |
---|---|---|---|
7:6 | NA | 0 | Reserved |
5 | PLL1R_RST | 0 | When set, PLL1 R divider will be held in reset. PLL1 will never lock with PLL1R_RST = 1. This bit is used in when synchronizing the PLL1 R divider. 0: PLL1 R divider normal operation. 1: PLL1 R divider held in reset. |
4:0 | NA | 0 | Reserved |