JAJSJN4C May 2020 – November 2022 LMK04832-SP
PRODUCTION DATA
The LMK04832 device is programmed using 24-bit registers. Each register consists of a 1-bit command field (R/W), a 15-bit address field (A14 to A0) and a 8-bit data field (D7 to D0). The contents of each register is clocked in MSB first (R/W), and the LSB (D0) last. During programming, the CS* signal is held low. The serial data is clocked in on the rising edge of the SCK signal. After the LSB is clocked in, the CS* signal goes high to latch the contents into the shift register. TI recommends to program registers in numeric order (for example, 0x000 to 0x555 with exceptions noted in the Section 8.5.1). Each register consists of one or more fields which control the device functionality. See the Section 6.5 section and Figure 6-1 for timing details.