JAJSJN4C May 2020 – November 2022 LMK04832-SP
PRODUCTION DATA
Figure 8-12 illustrates the use case of nested 0-delay dual loop mode. This configuration is similar to the dual PLL in Figure 8-10 except that the feedback to the first PLL is driven by a clock output. The PLL2 reference OSCin is not deterministic to the CLKin or feedback clock.