JAJSFI6C Februray 2017 – May 2018 LMK04832
PRODUCTION DATA.
This register controls the digital delay for the device clock outputs.
MSB | LSB |
---|---|
0x0102[2:3] = DCLK0_1_DDLY[9:8] | 0x101[7:0] = DCLK0_1_DDLY[7:0] |
0x010A[2:3] = DCLK2_3_DDLY[9:8] | 0x109[7:0] = DCLK2_3_DDLY[7:0] |
0x0112[2:3] = DCLK4_5_DDLY[9:8] | 0x111[7:0] = DCLK4_5_DDLY[7:0] |
0x011A[2:3] = DCLK6_7_DDLY[9:8] | 0x119[7:0] = DCLK6_7_DDLY[7:0] |
0x0122[2:3] = DCLK8_9_DDLY[9:8] | 0x121[7:0] = DCLK8_9_DDLY[7:0] |
0x012A[2:3] = DCLK10_11_DDLY[9:8] | 0x129[7:0] = DCLK10_11_DDLY[7:0] |
0x0132[2:3] = DCLK12_13_DDLY[9:8] | 0x131[7:0] = DCLK12_13_DDLY[7:0] |
REGISTER | BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|---|
0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132 | 2:3 | DCLKX_Y_DDLY[9:8] | 10 (0x0A) | Static digital delay which takes effect after a SYNC. | |
0x101, 0x109, 0x111, 0x119, 0x121, 0x129, 0x131 | 7:0 | DCLKX_Y_DDLY[7:0] | |||
Field Value | Delay Values | ||||
0 (0x00) | Reserved | ||||
1 (0x01) | Reserved | ||||
... | ... | ||||
7 (0x07) | Reserved | ||||
8 (0x08) | 8 | ||||
9 (0x09) | 9 | ||||
... | ... | ||||
1022 (0x3FE) | 1022 | ||||
1023 (0x3FF) | 1023 |
Depending on the DCLK divide value, there may be an adjustment in phase delay required. Table 18 illustrate the impact of different divide values on the final digital delay.
Divide Value | Digital delay Adjustment |
---|---|
2, 3 | -2(1) |
4, 7 to 1023 | 0 |
5 | +3 |
6 | +1 |
For example, Table 19 illustrates a system with clock outputs having divide values /2,/4,/5 and /6 to share a common edge.
Divide Value | Programmed DDLY | Actual DDLY |
---|---|---|
2 | 13 | 11 |
4 | 11 | 11 |
5 | 8 | 11 |
6 | 10 | 11 |