JAJSFI6C Februray 2017 – May 2018 LMK04832
PRODUCTION DATA.
These registers control the analog delay properties for the device clocks.
BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|
7 | NA | 0 | Reserved | |
6 | NA | 1 | Reserved | |
5 | CLKoutX_SRC_MUX | 0 | Select CLKoutX clock source. Source must also be powered up.
0: Device Clock 1: SYSREF |
|
4 | CLKoutX_Y_PD | 0 | Power down the clock group defined by X and Y.
0: Enabled 1: Power down enter clock group X_Y. |
|
3 | DCLKX_BYP | 0 | Enable high performance bypass path for even clock outputs.
0: CLKoutX not in high performance bypass mode. CML is not valid for CLKoutX_FMT. 1: CLKoutX in high performance bypass mode. Only CML clock format is valid. |
|
2 | DCLKX_Y_DCC | 0 | Duty cycle correction for device clock divider. Required for half step.
0: No duty cycle correction. 1: Duty cycle correction enabled. |
|
1 | DCLKX_Y_POL | 0 | Invert polarity of device clock output. This also applies to CLKoutX in high performance bypass mode. Polarity invert is a method to get a half-step phase adjustment in high performance bypass mode or /1 divide value.
0: Normal polarity 1: Invert polarity |
|
0 | DCLKX_Y_HS | 0 | Sets the device clock half step value. Must be set to zero (0) for a divide of 1.
No effect if DCLKX_Y_DCC = 0. 0: No phase adjustment 1: Adjust device clock phase -0.5 clock distribution path cycles. |