JAJSFI6C Februray   2017  – May 2018 LMK04832

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics – Clock Output AC Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Charge Pump Current Specification Definitions
      1. 7.1.1 Charge Pump Output Current Magnitude Variation vs Charge Pump Output Voltage
      2. 7.1.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch
      3. 7.1.3 Charge Pump Output Current Magnitude Variation vs Ambient Temperature
    2. 7.2 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1  Differences to LMK0482x
      2. 8.1.2  Jitter Cleaning
      3. 8.1.3  JEDEC JESD204B Support
      4. 8.1.4  Clock Inputs
        1. 8.1.4.1 Three Redundant PLL1 Reference Inputs
        2. 8.1.4.2 PLL2 Reference Inputs
        3. 8.1.4.3 Clock Distribution Reference Input
      5. 8.1.5  VCXO Buffered Output
      6. 8.1.6  Frequency Holdover
      7. 8.1.7  Internal VCOs
      8. 8.1.8  External VCO Mode
      9. 8.1.9  Clock Distribution
        1. 8.1.9.1 Clock Divider
        2. 8.1.9.2 High Performance Divider Bypass Mode
        3. 8.1.9.3 SYSREF Clock Divider
        4. 8.1.9.4 Device Clock Delay
        5. 8.1.9.5 Dynamic Digital Delay
        6. 8.1.9.6 SYSREF Delay: Global and Local
        7. 8.1.9.7 Programmable Output Formats
        8. 8.1.9.8 Clock Output Synchronization
      10. 8.1.10 0-Delay
      11. 8.1.11 Status Pins
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Synchronizing PLL R Dividers
        1. 8.3.1.1 PLL1 R Divider Synchronization
        2. 8.3.1.2 PLL2 R Divider Synchronization
      2. 8.3.2 SYNC/SYSREF
      3. 8.3.3 JEDEC JESD204B
        1. 8.3.3.1 How to Enable SYSREF
          1. 8.3.3.1.1 Setup of SYSREF Example
          2. 8.3.3.1.2 SYSREF_CLR
        2. 8.3.3.2 SYSREF Modes
          1. 8.3.3.2.1 SYSREF Pulser
          2. 8.3.3.2.2 Continuous SYSREF
          3. 8.3.3.2.3 SYSREF Request
      4. 8.3.4 Digital Delay
        1. 8.3.4.1 Fixed Digital Delay
          1. 8.3.4.1.1 Fixed Digital Delay Example
        2. 8.3.4.2 Dynamic Digital Delay
        3. 8.3.4.3 Single and Multiple Dynamic Digital Delay Example
      5. 8.3.5 SYSREF to Device Clock Alignment
      6. 8.3.6 Input Clock Switching
        1. 8.3.6.1 Input Clock Switching - Manual Mode
        2. 8.3.6.2 Input Clock Switching - Pin Select Mode
        3. 8.3.6.3 Input Clock Switching - Automatic Mode
      7. 8.3.7 Digital Lock Detect
        1. 8.3.7.1 Calculating Digital Lock Detect Frequency Accuracy
      8. 8.3.8 Holdover
        1. 8.3.8.1 Enable Holdover
          1. 8.3.8.1.1 Fixed (Manual) CPout1 Holdover Mode
          2. 8.3.8.1.2 Tracked CPout1 Holdover Mode
        2. 8.3.8.2 During Holdover
        3. 8.3.8.3 Exiting Holdover
        4. 8.3.8.4 Holdover Frequency Accuracy and DAC Performance
      9. 8.3.9 PLL2 Loop Filter
    4. 8.4 Device Functional Modes
      1. 8.4.1 DUAL PLL
        1. 8.4.1.1 Dual Loop
        2. 8.4.1.2 Dual Loop With Cascaded 0-Delay
        3. 8.4.1.3 Dual Loop With Nested 0-Delay
      2. 8.4.2 Single PLL
        1. 8.4.2.1 PLL2 Single Loop
        2. 8.4.2.2 PLL2 With External VCO
      3. 8.4.3 Distribution Mode
    5. 8.5 Programming
      1. 8.5.1 Recommended Programming Sequence
    6. 8.6 Register Maps
      1. 8.6.1 Register Map for Device Programming
      2. 8.6.2 Device Register Descriptions
        1. 8.6.2.1 System Functions
          1. 8.6.2.1.1 RESET, SPI_3WIRE_DIS
          2. 8.6.2.1.2 POWERDOWN
          3. 8.6.2.1.3 ID_DEVICE_TYPE
          4. 8.6.2.1.4 ID_PROD
          5. 8.6.2.1.5 ID_MASKREV
          6. 8.6.2.1.6 ID_VNDR
        2. 8.6.2.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
          1. 8.6.2.2.1 DCLKX_Y_DIV
          2. 8.6.2.2.2 DCLKX_Y_DDLY
          3. 8.6.2.2.3 CLKoutX_Y_PD, CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKX_Y_DDLY_PD, DCLKX_Y_DDLY[9:8], DCLKX_Y_DIV[9:8]
          4. 8.6.2.2.4 CLKoutX_SRC_MUX, CLKoutX_Y_PD, DCLKX_Y_BYP, DCLKX_Y_DCC, DCLKX_Y_POL, DCLKX_Y_HS
          5. 8.6.2.2.5 CLKoutY_SRC_MUX, SCLKX_Y_PD, SCLKX_Y_DIS_MODE, SCLKX_Y_POL, SCLKX_Y_HS
          6. 8.6.2.2.6 SCLKX_Y_ADLY_EN, SCLKX_Y_ADLY
          7. 8.6.2.2.7 SCLKX_Y_DDLY
          8. 8.6.2.2.8 CLKoutY_FMT, CLKoutX_FMT
        3. 8.6.2.3 SYSREF, SYNC, and Device Config
          1. 8.6.2.3.1  VCO_MUX, OSCout_MUX, OSCout_FMT
          2. 8.6.2.3.2  SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX
          3. 8.6.2.3.3  SYSREF_DIV
          4. 8.6.2.3.4  SYSREF_DDLY
          5. 8.6.2.3.5  SYSREF_PULSE_CNT
          6. 8.6.2.3.6  PLL2_RCLK_MUX, PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN
          7. 8.6.2.3.7  PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
          8. 8.6.2.3.8  DDLYdSYSREF_EN, DDLYdX_EN
          9. 8.6.2.3.9  DDLYd_STEP_CNT
          10. 8.6.2.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
          11. 8.6.2.3.11 SYNC_DISSYSREF, SYNC_DISX
          12. 8.6.2.3.12 PLL1R_SYNC_EN, PLL1R_SYNC_SRC, PLL2R_SYNC_EN
        4. 8.6.2.4 (0x146 - 0x149) CLKin Control
          1. 8.6.2.4.1 CLKin_SEL_PIN_EN, CLKin_SEL_PIN_POL, CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
          2. 8.6.2.4.2 CLKin_SEL_AUTO_REVERT_EN, CLKin_SEL_AUTO_EN, CLKin_SEL_MANUAL, CLKin1_DEMUX, CLKin0_DEMUX
          3. 8.6.2.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
          4. 8.6.2.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
        5. 8.6.2.5 RESET_MUX, RESET_TYPE
        6. 8.6.2.6 (0x14B - 0x152) Holdover
          1. 8.6.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
          2. 8.6.2.6.2 MAN_DAC
          3. 8.6.2.6.3 DAC_TRIP_LOW
          4. 8.6.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
          5. 8.6.2.6.5 DAC_CLK_CNTR
          6. 8.6.2.6.6 CLKin_OVERRIDE, HOLDOVER_EXIT_MODE, HOLDOVER_PLL1_DET, LOS_EXTERNAL_INPUT, HOLDOVER_VTUNE_DET, CLKin_SWITCH_CP_TRI, HOLDOVER_EN
          7. 8.6.2.6.7 HOLDOVER_DLD_CNT
        7. 8.6.2.7 (0x153 - 0x15F) PLL1 Configuration
          1. 8.6.2.7.1 CLKin0_R
          2. 8.6.2.7.2 CLKin1_R
          3. 8.6.2.7.3 CLKin2_R
          4. 8.6.2.7.4 PLL1_N
          5. 8.6.2.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
          6. 8.6.2.7.6 PLL1_DLD_CNT
          7. 8.6.2.7.7 HOLDOVER_EXIT_NADJ
          8. 8.6.2.7.8 PLL1_LD_MUX, PLL1_LD_TYPE
        8. 8.6.2.8 (0x160 - 0x16E) PLL2 Configuration
          1. 8.6.2.8.1 PLL2_R
          2. 8.6.2.8.2 PLL2_P, OSCin_FREQ, PLL2_REF_2X_EN
          3. 8.6.2.8.3 PLL2_N_CAL
          4. 8.6.2.8.4 PLL2_N
          5. 8.6.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
          6. 8.6.2.8.6 PLL2_DLD_CNT
          7. 8.6.2.8.7 PLL2_LD_MUX, PLL2_LD_TYPE
        9. 8.6.2.9 (0x16F - 0x555) Misc Registers
          1. 8.6.2.9.1 PLL2_PRE_PD, PLL2_PD
          2. 8.6.2.9.2 PLL1R_RST
          3. 8.6.2.9.3 CLR_PLL1_LD_LOST, CLR_PLL2_LD_LOST
          4. 8.6.2.9.4 RB_PLL1_LD_LOST, RB_PLL1_LD, RB_PLL2_LD_LOST, RB_PLL2_LD
          5. 8.6.2.9.5 RB_DAC_VALUE (MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
          6. 8.6.2.9.6 RB_DAC_VALUE
          7. 8.6.2.9.7 RB_HOLDOVER
          8. 8.6.2.9.8 SPI_LOCK
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Digital Lock Detect Frequency Accuracy
        1. 9.1.1.1 Minimum Lock Time Calculation Example
      2. 9.1.2 Driving CLKin AND OSCin Inputs
        1. 9.1.2.1 Driving CLKin and OSCin PINS With a Differential Source
        2. 9.1.2.2 Driving CLKin Pins With a Single-Ended Source
      3. 9.1.3 OSCin Doubler for Best Phase Noise Performance
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
          1. 9.2.2.1.1 Clock Architect
        2. 9.2.2.2 Device Configuration and Simulation
        3. 9.2.2.3 Device Programming
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Pin Connection Recommendations
  10. 10Power Supply Recommendations
    1. 10.1 Current Consumption
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Management
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 Clock Architect
        2. 12.1.1.2 PLLatinum Sim
        3. 12.1.1.3 TICS Pro
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION(1)
ICC_PD Power Down Supply Current 1.5 3 mA
ICC_JESD204B_ALL Supply Current for JESD204B use case during JESD204B synchronization VCO = 2949.12 MHz
Dual Loop (15) 		4 CML 32 mA clocks in bypass
3 LVDS clock /12
4 SYSREF as LCPECL
3 SYSREF as LVDS		 930 1120 mA
ICC_JESD204B_LOW Supply Current for JESD204B use case during JESD204B steady state while holding SYSREF as low in DC coupled configuration. (15)
4 CML 32 mA clocks in bypass
3 LVDS clock /12
4 SYSREF as LCPECL (low state)
3 SYSREF as LVDS (low state)		 780 940 mA
ICC_JESD204B_VCM Supply Current for JESD204B use case during JESD204B steady state while setting SYSREF outputs as Vcm. (15) 4 CML 32 mA clocks in bypass
3 LVDS clock /12
7 SYSREF outputs powered down		 675 810 mA
CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS
fCLKinX_LOS Clock Input LOS
(CLKin0/1/2)		 LOS_EN = 1 0.001 250 MHz
fCLKin0_PLL1_MOS Clock Input Frequency for PLL1 Reference (CLKin0/1/2)
CLKinX_TYPE = 1 (MOS)		 CLKin0_OUT_MUX = 2 (PLL1) 0.001 250 MHz
fCLKin1_PLL1_MOS CLKin1_OUT_MUX = 2 (PLL1) MHz
fCLKin2_PLL1_MOS OSCout_FMT = 0 (Power down) MHz
fCLKin0_PLL1 Clock Input Frequency for PLL1 Reference (CLKin0/1/2)
CLKinX_TYPE = 0 (Bipolar)		 CLKin0_OUT_MUX = 2 (PLL1) 0.001 750 MHz
fCLKin1_PLL1 CLKin1_OUT_MUX = 2 (PLL1)
fCLKin2_PLL1 OSCout_FMT = 0 (Power down)
fCLKin0_PLL2 Clock Input Frequency for PLL2 Reference (CLKin0/1/2)
CLKinX_TYPE = 0 (Bipolar)		 CLKin0_OUT_MUX = 2 (PLL1)
PLL2R_CLK_MUX = 1 (PLL1 CLKinX)		 500 MHz
fCLKin1_PLL2 CLKin1_OUT_MUX = 2 (PLL1)
PLL2R_CLK_MUX = 1 (PLL1 CLKinX)
fCLKin2_PLL2 OSCout_FMT = 0 (Power down)
PLL2R_CLK_MUX = 1 (PLL1 CLKinX)
fCLKin1_FB Clock Input Frequency for 0-delay with external feedback (CLKin1) CLKin1_OUT_MUX = 1 (FB Mux)
CLKin1_TYPE = 0 (Bipolar)		 0.001 750 MHz
fCLKin1_Fin Clock Input Frequency for external VCO or distribution mode (CLKin1) CLKin1_OUT_MUX = 0 (Fin)
CLKin1_TYPE = 0 (Bipolar)		 0.001 3250 MHz
SLEWCLKin Clock Input Slew Rate(2) 20% to 80% 0.15 0.5 V/ns
VIDCLKin_AC Differential Clock Input Voltage(3) AC-coupled 0.125 1.55 |V|
VSSCLKin_AC 0.25 3.1 Vpp
VCLKin Clock Input Single-ended Input Voltage AC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
CLKinX_TYPE = 0 (Bipolar)		 0.5 2.4 Vpp
|VCLKinX-offset| DC offset voltage between CLKinX/CLKinX* (CLKinX* - CLKinX) Each pin AC-coupled, CLKin0/1/2
CLKinX_TYPE = 0 (Bipolar)		 0 |mV|
Each pin AC-coupled, CLKin0/1
CLKinX_TYPE = 1 (MOS)		 55 |mV|
DC offset voltage between CLKin2/CLKin2* (CLKin2* - CLKin2) Each pin AC-coupled
CLKinX_TYPE = 1 (MOS)		 20 |mV|
VCLKinVIH High Input Voltage DC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
CLKinX_TYPE = 1 (MOS)		 2 Vcc V
VCLKinVIL Low Input Voltage 0 0.4 V
PLL1 SPECIFICATIONS
fPD1 PLL1 Phase Detector Frequency 40 MHz
ICPout1SOURCE PLL1 Charge Pump Source Current(4) VCPout1 = Vcc/2, PLL1_CP_GAIN = 0 50 µA
VCPout1 = Vcc/2, PLL1_CP_GAIN = 1 150
VCPout1 = Vcc/2, PLL1_CP_GAIN = 2 250
. . . . . .
VCPout1 = Vcc/2, PLL1_CP_GAIN = 14 1450
VCPout1 = Vcc/2, PLL1_CP_GAIN = 15 1550
ICPout1SINK PLL1 Charge Pump Sink Current(4) VCPout1 = Vcc/2, PLL1_CP_GAIN = 0 -50 µA
VCPout1 = Vcc/2, PLL1_CP_GAIN = 1 -150
VCPout1 = Vcc/2, PLL1_CP_GAIN = 2 -250
. . . . . .
VCPout1 = Vcc/2, PLL1_CP_GAIN = 14 -1450
VCPout1 = Vcc/2, PLL1_CP_GAIN = 15 -1550
ICPout1%MIS Charge Pump Sink / Source Mismatch VCPout1 = Vcc/2, TA = 25 °C 1% 10%
ICPout1%VTUNE Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage 0.5 V < VCPout1 < VCC - 0.5 V TA = 25 °C 4%
ICPout1%TEMP Charge Pump Current vs. Temperature Variation 4%
ICPout1TRI Charge Pump TRI-STATE Leakage Current 0.5 V < VCPout1 < VCC - 0.5 V 5 nA
PN10 kHz(6) PLL 1/f Noise at 10 kHz offset. Normalized to 1 GHz Output Frequency PLL1_CP_GAIN = 50 µA -113 dBc/Hz
PLL1_CP_GAIN = 450 µA -117
PLL1_CP_GAIN = 1550 µA -119
PN1 Hz(7) Normalized Phase Noise Contribution PLL1_CP_GAIN = 50 µA -217 dBc/Hz
PLL1_CP_GAIN = 450 µA -224
PLL1_CP_GAIN = 1550 µA -225
OSCin INPUT CLOCK SPECIFICATIONS
fOSCin PLL2 Reference Input 500 MHz
SLEWOSCin PLL2 Reference Clock minimum slew rate on OSCin(2) 20% to 80% 0.15 0.5 V/ns
VOSCin Input Voltage for OSCin or OSCin* AC coupled; Single-ended
(Unused pin AC-coupled to GND)		 0.2 2.4 Vpp
VIDOSCin Differential voltage swing(3) AC-coupled 0.2 1.55 |V|
VSSOSCin 0.4 3.1 Vpp
|VOSCin-offset| DC offset voltage between OSCin/OSCin* (OSCinX* - OSCinX) Each pin AC-coupled 20 |mV|
fdoubler_max Doubler input frequency EN_PLL2_REF_2X = 1(5);
OSCin Duty Cycle 40% to 60%		 320 MHz
PLL2 SPECIFICATIONS
fPD2 Phase Detector Frequency 320 MHz
ICPout2 SOURCE PLL2 Charge Pump Source Current(4) VCPout2 = VCC/2, PLL2_CP_GAIN = 2 1600 µA
VCPout2 = VCC/2, PLL2_CP_GAIN = 3 3200
ICPout2 SINK PLL2 Charge Pump Sink Current(4) VCPout2 = VCC/2, PLL2_CP_GAIN = 2 -1600 µA
VCPout2 = VCC/2, PLL2_CP_GAIN = 3 -3200
ICPout2%MIS Charge Pump Sink / Source Mismatch VCPout2 = Vcc/2, TA = 25 °C 1% 10%
ICPout2%VTUNE Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage 0.5 V < VCPout2 < VCC - 0.5 V
TA = 25 °C		 4%
ICPout2%TEMP Charge Pump Current vs. Temperature Variation 4%
ICPout2 TRI Charge Pump TRI-STATE Leakage Current 0.5 V < VCPout2 < VCC - 0.5 V 10 nA
PN10 kHz(6) PLL 1/f Noise at 10 kHz offset. Normalized to 1 GHz Output Frequency PLL2_CP_GAIN = 3200 µA -128 dBc/Hz
PN1 Hz(7) Normalized Phase Noise Contribution PLL2_CP_GAIN = 3200 µA -230 dBc/Hz
INTERNAL VCO SPECIFICATIONS
fVCO LMK04832 VCO Tuning Range VCO0 2440 2580 MHz
VCO1 2945 3255
KVCO LMK04832 Vtune Tuning Sensitivity VCO0 2440 MHz -11.8 MHz/V
2580 MHz -14.5
VCO1 2945 MHz -22.9
3255 MHz -31.4
|ΔTCL| Allowable Temperature Drift for Continuous Lock(8) After programming for lock, no changes to output configuration are permitted to assure continuous lock 125 °C
L(f)VCO Open-loop phase noise VCO0 at
2440 MHz		 1 kHz -55 dBc/Hz
10 kHz -86.3
100 kHz -115.2
800 kHz -136.3
1 MHz -137.6
VCO0 at
2580 MHz		 1 kHz -53.3 dBc/Hz
10 kHz -85
100 kHz -114.3
800 kHz -135.3
1 MHz -136.9
VCO1 at
2945 MHz		 1 kHz -49.2 dBc/Hz
10 kHz -81.1
100 kHz -111.1
800 kHz -133.8
1 MHz -135.9
VCO1 at
3250 MHz		 1 kHz -46.6 dBc/Hz
10 kHz -78.9
100 kHz -108.9
800 kHz -131.7
1 MHz -133.3
CLOCK OUTPUT NOISE FLOOR
L(f)CLKout 245.76 MHz Noise Floor
20 MHz Offset		 LVDS CLKoutX_Y_ODL=1 -159.5 dBc/Hz
L(f)CLKout HSDS 6 mA CLKoutX_Y_ODL=1 -161.5
L(f)CLKout HSDS 8 mA CLKoutX_Y_ODL=1 -162.5
L(f)CLKout LCPECL CLKoutX_Y_ODL=1 -162.5
L(f)CLKout LVPECL 1.6 Vpp CLKoutX_Y_ODL=1 -162
L(f)CLKout LVPECL 2 Vpp CLKoutX_Y_ODL=1 -163
L(f)CLKout CML 16 mA, odd CLKoutY
DC bias: 50 Ω to Vcc		 CLKoutX_Y_ODL=1 -162.5
L(f)CLKout CML 24 mA, odd CLKoutY
DC bias: 50 Ω to Vcc		 CLKoutX_Y_ODL=1 -162.5
L(f)CLKout CML 32 mA, odd CLKoutY
DC bias: 50 Ω to Vcc		 CLKoutX_Y_ODL=1 -163
L(f)CLKout LVCMOS CLKoutX_Y_ODL=1 -160
L(f)CLKout 3.2 GHz Noise Floor
20 MHz Offset		 CML 16 mA, even CLKoutX
DC bias: 68 nH to 20 Ω to Vcc		 CLKoutX_Y_IDL=1 -155.5 dBc/Hz
L(f)CLKout CML 24 mA, even CLKoutX
DC bias: 68 nH to 20 Ω to Vcc		 CLKoutX_Y_IDL=1 -156
L(f)CLKout CML 32 mA, even CLKoutX
DC bias: 68 nH to 20 Ω to Vcc		 CLKoutX_Y_IDL=1 -156.5
CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS
L(f)CLKout VCO0 SSB Phase Noise 245.76 MHz(9)
Doubler disabled		 Offset = 1 kHz -125 dBc/Hz
Offset = 10 kHz -134
Offset = 100 kHz -137
Offset = 1 MHz -154
L(f)CLKout VCO1 SSB Phase Noise 245.76 MHz(9)
Doubler disabled		 Offset = 1 kHz -125 dBc/Hz
Offset = 10 kHz -135
Offset = 100 kHz -137
Offset = 1 MHz -151
CLKout CLOSED LOOP JITTER SPECIFICATIONS
JCLKout VCO0, fCLKout = 2500 MHz(23)
Integrated RMS Jitter		 PDF = 312.5 MHz
BW = 12 kHz to 20 MHz		 54 fs rms
PDF = 312.5 MHz
BW = 100 Hz to 100 MHz		 64 fs rms
VCO1, fCLKout = 3200 MHz(23)
Integrated RMS Jitter		 PDF = 320 MHz 
BW = 12 kHz to 20 MHz		 61 fs rms
PDF = 320 MHz 
BW = 100 Hz to 100 MHz		 67 fs rms
JCLKout VCO0, fCLKout = 2457.6 MHz
Integrated RMS Jitter(9) 		PDF = 245.76 MHz (Doubler enabled)
BW = 12 kHz to 20 MHz		 55 fs rms
VCO0, fCLKout = 2457.6 MHz
Integrated RMS Jitter(9) 		PDF = 122.88 MHz
BW = 12 kHz to 20 MHz		 70 fs rms
VCO1, fCLKout = 2949.12 MHz
Integrated RMS Jitter(9) 		PDF = 245.76 (Doubler enabled)
BW = 12 kHz to 20 MHz		 60 fs rms
VCO1, fCLKout = 2949.12 MHz
Integrated RMS Jitter(9) 		PDF = 122.88 MHz
BW = 12 kHz to 20 MHz
75 fs rms
DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY
fOSCout OSCout default frequency(10) 500 MHz
CLOCK SKEW(11)
|TSKEW| Maximum skew CLKoutX to CLKoutX
FCLK = 1.6 GHz, RL = 100 Ω AC-coupled		 Any even CLKoutX, same format(20)
Device Clock
DCLKX_Y_BYP = 1		 60 |ps|
|TSKEW| Maximum skew for CLKoutX to CLKoutX or CLKoutY to CLKoutY
FCLK = 250 MHz, RL = 100 Ω AC-coupled		 Even to even or odd to odd clock, same format(21)
Device clock
DCLKX_Y_BYP = 0
DCLKX_Y_DIV = 12		 60 |ps|
|TSKEW| Maximum skew for any CLKoutX or Y to any CLKoutX or Y
FCLK = 250 MHz, RL = 100 Ω AC-coupled		 Any output, same format(21)
Device clock
DCLKX_Y_BYP = 0
DCLKX_Y_DIV = 12		 100 |ps|
|TSKEW| Delay from CLKoutX to CLKoutY in same pair
FCLK = 250 MHz, RL = 100 Ω AC-coupled		 Same pair of device clocks, same format(21) 35 ps
CML 32 mA CLOCK OUTPUTS (CLKoutX/Y)
TR / TF 20% to 80% Output Rise/Fall RL = AC-coupled 100 Ω, 250 MHz
Odd CLKoutY, CLKoutX_Y_ODL = 1
DC Bias, 50 ohm to Vcc		 135 ps
VOH Output High Voltage T = 25 °C, DC measurement
Termination 50-Ω pull up to Vcc		 Vcc V
VOL Output Low Voltage Vcc - 1.66
VOD Differential Output Voltage 1660 |mV|
VOD Differential Output Voltage DC bias is 50-Ω pull up to Vcc
RL = AC-coupled 100 Ω		 250 MHz(16) 1070 |mV|
DC bias is 68-nH to 20-Ω to Vcc
RL = AC-coupled 100 Ω		 2.5 GHz(13) 765
2.5 GHz(14) 550
3.2 GHz(13) 610
3.2 GHz(14) 385
CML 24 mA CLOCK OUTPUTS (CLKoutX/Y)
TR / TF 20% to 80% Output Rise/Fall RL = AC-coupled 100 Ω, 250 MHz
Odd CLKoutY, CLKoutX_Y_ODL = 1
DC Bias, 50 ohm to Vcc		 125 ps
VOH Output High Voltage T = 25 °C, DC measurement
Termination 50-Ω pull up to Vcc		 Vcc V
VOL Output Low Voltage Vcc - 1.26
VOD Differential Output Voltage 1260 |mV|
VOD Differential Output Voltage DC bias is 50-Ω pull up to Vcc
RL = AC-coupled 100 Ω		 250 MHz(16) 815 |mV|
DC bias is 68-nH to 20-Ω to Vcc
RL = AC-coupled 100 Ω		 2.5 GHz(13) 595
2.5 GHz(14) 445
3.2 GHz(13) 480
3.2 GHz(14) 330
CML 16 mA CLOCK OUTPUTS (CLKoutX/Y)
TR / TF 20% to 80% Output Rise/Fall RL = AC-coupled 100 Ω, 250 MHz
Odd CLKoutY, CLKoutX_Y_ODL = 1
DC Bias, 50 ohm to Vcc		 120 ps
VOH Output High Voltage T = 25 °C, DC measurement
Termination is 50-Ω pull up to Vcc		 Vcc V
VOL Output Low Voltage Vcc - 0.84
VOD Differential Output Voltage 840 |mV|
VOD Differential Output Voltage DC bias is 50-Ω pull up to Vcc
RL = AC-coupled 100 Ω		 250 MHz(16) 550 |mV|
VOD DC bias is 68-nH to 20-Ω to Vcc
RL = AC-coupled 100 Ω		 2.5 GHz(13) 400  
VOD 2.5 GHz(14) 325  
VOD 3.2 GHz(13) 325  
VOD 3.2 GHz(14) 250  
LVPECL CLOCK OUTPUT (CLKoutX/Y, OSCout)
TR / TF 20% to 80% Output Rise/Fall RL = AC-coupled 100 Ω, 250 MHz 140 ps
LVPECL 2000 mVpp CLOCK OUTPUTS (CLKoutX/Y, OSCout)
VOH Output High Voltage DC Measurement
Termination = 50-Ω to VCC - 2.0 V		 VCC - 1 V
VOL Output Low Voltage VCC - 2 V
VOD Output Voltage(3) 1000 |mV|
VOD Differential Output Voltage Em = 120 Ω to ground
Termination = AC-coupled 100 Ω		 250 MHz(19) 925 |mV|
2.5 GHz(17) 585
2.5 GHz(18) 545
3.2 GHz(17) 415
3.2 GHz(18) 370
LVPECL 1600 mVpp CLOCK OUTPUTS (CLKoutX/Y, OSCout)
VOH Output High Voltage DC Measurement
Termination = 50-Ω to VCC - 2.0 V		 VCC - 1 V
VOL Output Low Voltage VCC - 1.8 V
VOD Output Voltage(3) 800 |mV|
VOD Differential Output Voltage Em = 120 Ω to ground
Termination = AC-coupled 100 Ω		 250 MHz(19) 760 |mV|
2.5 GHz(17) 510
2.5 GHz(18) 480
3.2 GHz(17) 370
3.2 GHz(18) 340
LCPECL CLOCK OUTPUT (CLKoutX/Y, OSCout)
TR / TF 20% to 80% Output Rise/Fall RL = AC-coupled 100 Ω
DC bias = 120 Ω to GND		 135 ps
VOH Output High Voltage DC Measurement
Termination = 50-Ω to 0.5 V		 1.6 V
VOL Output Low Voltage 0.6 V
VOD Output Voltage(3) 1000 |mV|
HSDS 8 mA CLOCK OUTPUTS (CLKoutX/Y)
TR / TF 20% to 80% Output Rise/Fall RL = 100 Ω, 250 MHz 170 ps
VOH Output High Voltage DC Measurement
Termination = 50-Ω to VCC - 1.64 V		 VCC - 0.95 V
VOL Output Low Voltage VCC - 1.7 V
VOD Output Voltage(3) 750 |mV|
ΔVOD Change in Magnitude of VOD for complementary output states -115 115 mV
HSDS 6 mA CLOCK OUTPUTS (CLKoutX/Y)
TR / TF 20% to 80% Output Rise RL = 100 Ω, 250 MHz 170 ps
VOH Output High Voltage DC Measurement
Termination = 50-Ω to VCC - 1.42 V		 VCC - 0.9 V
VOL Output Low Voltage VCC - 1.5 V
VOD Output Voltage(3) 600 |mV|
ΔVOD Change in Magnitude of VOD for complementary output states -80 80 mV
LVDS CLOCK OUTPUTS (CLKoutX/Y, OSCout)
TR / TF 20% to 80% Output Rise RL = 100 Ω, 250 MHz 175 ps
VOD Differential Output Voltage T = 25 °C, DC measurement
AC-coupled to receiver input
RL = 100-Ω differential termination		 400 |mV|
ΔVOD Change in Magnitude of VOD for complementary output states -60 60 mV
VOS Output Offset Voltage 1.125 1.25 1.375 V
ΔVOS Change in VOS for complementary output states 35 |mV|
ISA ISB Output short circuit current - single-ended Single-ended output shorted to GND
T = 25 °C		 -24 24 mA
LVCMOS CLOCK OUTPUTS (CLKout8/10/Y, OSCout)
fCLKout Maximum Frequency 5 pF Load 250 MHz
VOH Output High Voltage 1 mA Load Vcc - 0.1 V
VOL Output Low Voltage 1 mA Load 0.1 V
IOH Output High Current (Source) VCC = 3.3 V, VO = 1.65 V -28 mA
IOL Output Low Current (Sink) VCC = 3.3 V, VO = 1.65 V 28 mA
DUTYCLK Output Duty Cycle(12)(22) VCC/2 to VCC/2, FCLK = 100 MHz, T = 25°C 50 %
DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO)
VOH High-Level Output Voltage IOH = -500 µA
CLKin_SELX_TYPE = 3 or 4
Status_LDX_TYPE = 3 or 4
RESET_TYPE = 3 or 4		 VCC - 0.4 V
VOL Low-Level Output Voltage IOL = 500 µA
CLKin_SELX_TYPE = 3, 4, or 6
Status_LDX_TYPE = 3, 4, or 6
RESET_TYPE = 3, 4, or 6		 0.4 V
DIGITAL OUTPUTS (SDIO)
VOH High-Level Output Voltage IOH = -500 µA; During SPI read.
SDIO_RDBK_TYPE = 0		 VCC - 0.4 V
VOL Low-Level Output Voltage IOL = 500 µA; During SPI read.
SDIO_RDBK_TYPE = 0 or 1		 0.4 V
DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, and CS*)
VIH High-Level Input Voltage 1.2 V
VIL Low-Level Input Voltage 0.5 V
DIGITAL INPUT (CLKinX_SEL)
IIH High-Level Input Current VIH = VCC CLKin_SELX_TYPE = 0 (High Impedance) -5 5 µA
CLKin_SELX_TYPE = 1 (Pull up) -5 5
CLKin_SELX_TYPE = 2 (Pull-down) 10 80
IIL Low-Level Input Current VIL = 0 V CLKin_SELX_TYPE = 0 (High Impedance) -5 5 µA
CLKin_SELX_TYPE = 1 (Pull up) -40 -5
CLKin_SELX_TYPE = 2 (Pull-down) -5 5
DIGITAL INPUT (RESET/GPO)
IIH High-Level Input Current VIH = VCC RESET_TYPE = 2 (Pull-down) 10 80 µA
IIL Low-Level Input Current VIL = 0 V RESET_TYPE = 0 (High Impedance) -5 5 µA
RESET_TYPE = 1 (Pull up) -40 -5
RESET_TYPE = 2 (Pull-down) -5 5
DIGITAL INPUT (SYNC)
IIH High-Level Input Current VIH = VCC 25 µA
IIL Low-Level Input Current VIL = 0 V -5 5 µA
DIGITAL INPUTS (SCK, SDIO, CS*)
IIH High-Level Input Current VIH = VCC -5 5 µA
IIL Low-Level Input Current VIL = 0 V -5 5 µA
(1) Use the TICS Pro tool to calculate Icc for a specific configuration.
(2) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
(3) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
(4) This parameter is programmable
(5) The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.
(6) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10 kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10 kHz = LPLL_flicker(10 kHz) - 20 log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low-power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f).
(7) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1 HZ = LPLL_flat(f) - 20 log(N) - 10 log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
(8) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of – 40 °C to 85 °C without violating specifications.
(9) Dual Loop, OSCin reference is a 122.88 MHz Crystek 603281 VCXO. Data collected using a MACOM H-183-4 Hybrid Junction for differential to single ended converstion.  PLL2_CP = 3.2 mA.  PLL2 Loop filter is C1i = 60 pF, C1 (external) = 4.7 pF, R2 = 820 Ω (external), C2 = 3.9 nF (external), R3 = 2.4 kΩ, C3 = 50 pF, R4 = 200 Ω, C4 = 10 pF.  PLL1_CP = 450 µA with a narrow loop bandwidth. CLKoutX_Y_IDL = 0, CLKoutX_Y_ODL = 1. Even CLKout with LVPECL20 format using 120-Ω to GND.
(10) OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port.
(11) Equal loading and identical clock configuration on each clock input and/or output is required for skew, setup, and hold specifications to be valid.
(12) For OSCout when driven by OSCin, assumes OSCin has 50% input duty cycle.
(13) Even clock outputs (CLKoutX). CLKoutX_Y_IDL=1, CLKoutX_Y_ODL=X.
(14) Odd clock outputs (CLKoutY).  CLKoutX_Y_IDL=X, CLKoutX_Y_ODL=1
(15) LCPECL clocks have 120 Ω emitter resistors.  OSCout LVPECL clock uses 240 Ω ohm emitter resistors.  Other settings include CLKoutX_Y_IDL = 0, CLKoutX_Y_ODL = 0, DCLKX_Y_DCC = 0.  SCLK_X_Y_ADLY_EN = 0.
(16) For even and odd outputs CLKoutX_Y_IDL=0.  For even outputs CLKoutX_Y_ODL=X and for odd CLKoutX_Y_ODL=1.
(17) Even clock outputs (CLKoutX). CLKoutX_Y_IDL=X, CLKoutX_Y_ODL=1.
(18) Odd clock outputs (CLKoutY).  CLKoutX_Y_IDL=X, CLKoutX_Y_ODL=1
(19) CLKoutX_Y_IDL=X and CLKoutX_Y_ODL=X.
(20) Valid for CML 32 mA, CML 24 mA, CML 16 mA.  CML DC bias is 50 ohms to Vcc or 68 nH to 20 Ω to Vcc.
(21) Valid for HSDS 8 mA, HSDS 6 mA, LVDS.  LVPECL20, LVPECL16, LCPECL with 120 Ω emitter resistor to ground.
(22) For any device clock with an odd divide value, assumes selected clock output has DCLKX_Y_DCC = 1 to enable duty cycle correction.
(23) Single Loop, OSCin reference is R&S SMA100B Signal Generator with option SMAB-B711 through Prodyn BIB-100G Balun to OSCin.  Data collected using a MACOM H-183-4 Hybrid Junction for differential to single ended converstion.  PLL2 Loop filter is C1 = 60 pF, R2 = 470 Ω (external), C2 = 150 nF (external), R3 = 2.4 kΩ, C3 = 50 pF, R4 = 200 Ω, C4 = 10 pF, PLL2_CP = 3.2 mA. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0;  Even CLKout with CML 32 mA format using DC bias 68-nH to 20-Ω to Vcc.