JAJSFI6C Februray 2017 – May 2018 LMK04832
PRODUCTION DATA.
These bits are used when synchronizing PLL1 and PLL2 R dividers. Refer to Synchronizing PLL R Dividers for more information.
BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|
7 | NA | 0 | Reserved | |
6 | PLL1R_SYNC_EN | 0 | Enable synchronization for PLL1 R divider
0: Not enabled 1: Enabled |
|
5:4 | PLL1R_SYNC_SRC | 0 | Select the source for PLL1 R divider synchronization | |
Field Value | Definition | |||
0 (0x00) | Reserved | |||
1 (0x01) | SYNC Pin | |||
2 (0x02) | CLKin0 | |||
3 (0x03) | Reserved | |||
3 | PLL2R_SYNC_EN | 0 | Enable synchronization for PLL2 R divider. Synchronization for PLL2 R always comes from the SYNC pin.
0: Not enabled 1: Enabled |
|
2:0 | NA | 0 | Reserved |