JAJSFI6C Februray 2017 – May 2018 LMK04832
PRODUCTION DATA.
This register has CLKin_SEL0 controls.
BIT | NAME | POR DEFAULT | DESCRIPTION | ||
---|---|---|---|---|---|
7:6 | NA | 0 | Reserved | ||
5:3 | CLKin_SEL0_MUX | 0 | This set the output value of the CLKin_SEL0 pin. This register only applies if CLKin_SEL0_TYPE is set to an output mode | ||
Field Value | Output Format | ||||
0 (0x00) | Logic Low | ||||
1 (0x01) | CLKin0 LOS | ||||
2 (0x02) | CLKin0 Selected | ||||
3 (0x03) | DAC Locked | ||||
4 (0x04) | DAC Low | ||||
5 (0x05) | DAC High | ||||
6 (0x06) | SPI Readback | ||||
7 (0x07) | Reserved | ||||
2:0 | CLKin_SEL0_TYPE | 2 | This sets the IO type of the CLKin_SEL0 pin. | ||
Field Value | Configuration | Function | |||
0 (0x00) | Input | Input mode, see Input Clock Switching - Pin Select Mode for description of input mode. | |||
1 (0x01) | Input with pullup resistor | ||||
2 (0x02) | Input with pulldown resistor | ||||
3 (0x03) | Output (push-pull) | Output modes; the CLKin_SEL0_MUX register for description of outputs. | |||
4 (0x04) | Output inverted (push-pull) | ||||
5 (0x05) | Reserved | ||||
6 (0x06) | Output (open-drain) |