JAJSFI6C Februray 2017 – May 2018 LMK04832
PRODUCTION DATA.
This register has controls for enabling clock in switch events.
BIT | NAME | POR DEFAULT | DESCRIPTION |
---|---|---|---|
7 | NA | 0 | Reserved |
6 | CLKin
_OVERRIDE |
0 | When manual clock select is enabled, then CLKin_SEL_MANUAL = 0/1/2 selects a manual clock input. CLKin_OVERRIDE = 1 will force that clock input. CLKin_OVERRIDE = 1 is used with clock distribution mode for best performance.
0: Normal, no override. 1: Force select of only CLKin0/1/2 as specified by CLKin_SEL_MANUAL in manual mode. Dynamic digital delay will not operate. |
5 | HOLDOVER_
EXIT_MODE |
0 | 0: Exit based on LOS status. If clock is active by LOS, then begin exit.
1: Exit based on PLL1 DLD. When the PLL1 phase detector confirming valid clock. |
4 | HOLDOVER
_PLL1_DET |
0 | This enables the HOLDOVER when PLL1 lock detect signal transitions from high to low.
0: PLL1 DLD does not cause a clock switch event 1: PLL1 DLD causes a clock switch event |
3 | LOS_EXTERNAL_INPUT | 0 | Use external signals for LOS status instead of internal LOS circuitry. CLKin_SEL0 pin is used for CLKin0 LOS, CLKin_SEL1 pin is used for CLKin1 LOS, and Status_LD1 is used for CLKin2 LOS. For any of these pins to be valid, the corresponding _TYPE register must be programmed as an input.
0: Disabled 1: Enabled |
2 | HOLDOVER_
VTUNE_DET |
0 | Enables the DAC Vtune rail detector. When the DAC achieves a specified Vtune, if this bit is enabled, the current clock input is considered invalid and an input clock switch event is generated.
0: Disabled 1: Enabled |
1 | CLKin_SWITCH_CP_TRI | 0 | Enable clock switching with tri-stated charge pump.
0: Not enabled. 1: PLL1 charge pump tri-states during clock switching. |
0 | HOLDOVER_EN | 0 | Sets whether holdover mode is active or not.
0: Disabled 1: Enabled |