JAJSFI6C Februray 2017 – May 2018 LMK04832
PRODUCTION DATA.
MSB | LSB |
---|---|
0x160[3:0] / PLL2_R[11:8] | 0x161[7:0] / PLL2_R[7:0] |
This register contains the value of the PLL2 R divider.
REGISTER | BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|---|
0x160 | 7:4 | NA | 0 | Reserved | |
0x160 | 3:0 | PLL2_R[11:8] | 0 | Valid values for the PLL2 R divider. | |
Field Value | Divide Value | ||||
0 (0x00) | Not Valid | ||||
1 (0x01) | 1 | ||||
0x161 | 7:0 | PLL2_R[7:0] | 2 | 2 (0x02) | 2 |
3 (0x03) | 3 | ||||
... | ... | ||||
4,094 (0xFFE) | 4,094 | ||||
4,095 (0xFFF) | 4,095 |