JAJSFI6C Februray 2017 – May 2018 LMK04832
PRODUCTION DATA.
This register sets the output value of the Status_LD2 pin.
BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|
7:3 | PLL2_LD_MUX | 0 | This sets the output value of the Status_LD2 pin. | |
Field Value | MUX Value | |||
0 (0x00) | Logic Low | |||
1 (0x01) | PLL1 DLD | |||
2 (0x02) | PLL2 DLD | |||
3 (0x03) | PLL1 & PLL2 DLD | |||
4 (0x04) | Holdover Status | |||
5 (0x05) | DAC Locked | |||
6 (0x06) | Reserved | |||
7 (0x07) | SPI Readback | |||
8 (0x08) | DAC Rail | |||
9 (0x09) | DAC Low | |||
10 (0x0A) | DAC High | |||
11 (0x0B) | PLL1_N | |||
12 (0x0C) | PLL1_N/2 | |||
13 (0x0D) | PLL2_N | |||
14 (0x0E) | PLL2_N/2 | |||
15 (0x0F) | PLL1_R | |||
16 (0x10) | PLL1_R/2 | |||
17 (0x11) | PLL2_R(1) | |||
18 (0x12) | PLL2_R/2(1) | |||
2:0 | PLL2_LD_TYPE | 6 | Sets the IO type of the Status_LD2 pin. | |
Field Value | TYPE | |||
0 (0x00) | Reserved | |||
1 (0x01) | Reserved | |||
2 (0x02) | Reserved | |||
3 (0x03) | Output (push-pull) | |||
4 (0x04) | Output inverted (push-pull) | |||
5 (0x05) | Reserved | |||
6 (0x06) | Output (open drain) |