JAJSFI6C
Februray 2017 – May 2018
LMK04832
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
概略回路図
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Timing Diagram
6.8
Typical Characteristics – Clock Output AC Characteristics
7
Parameter Measurement Information
7.1
Charge Pump Current Specification Definitions
7.1.1
Charge Pump Output Current Magnitude Variation vs Charge Pump Output Voltage
7.1.2
Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch
7.1.3
Charge Pump Output Current Magnitude Variation vs Ambient Temperature
7.2
Differential Voltage Measurement Terminology
8
Detailed Description
8.1
Overview
8.1.1
Differences to LMK0482x
8.1.2
Jitter Cleaning
8.1.3
JEDEC JESD204B Support
8.1.4
Clock Inputs
8.1.4.1
Three Redundant PLL1 Reference Inputs
8.1.4.2
PLL2 Reference Inputs
8.1.4.3
Clock Distribution Reference Input
8.1.5
VCXO Buffered Output
8.1.6
Frequency Holdover
8.1.7
Internal VCOs
8.1.8
External VCO Mode
8.1.9
Clock Distribution
8.1.9.1
Clock Divider
8.1.9.2
High Performance Divider Bypass Mode
8.1.9.3
SYSREF Clock Divider
8.1.9.4
Device Clock Delay
8.1.9.5
Dynamic Digital Delay
8.1.9.6
SYSREF Delay: Global and Local
8.1.9.7
Programmable Output Formats
8.1.9.8
Clock Output Synchronization
8.1.10
0-Delay
8.1.11
Status Pins
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Synchronizing PLL R Dividers
8.3.1.1
PLL1 R Divider Synchronization
8.3.1.2
PLL2 R Divider Synchronization
8.3.2
SYNC/SYSREF
8.3.3
JEDEC JESD204B
8.3.3.1
How to Enable SYSREF
8.3.3.1.1
Setup of SYSREF Example
8.3.3.1.2
SYSREF_CLR
8.3.3.2
SYSREF Modes
8.3.3.2.1
SYSREF Pulser
8.3.3.2.2
Continuous SYSREF
8.3.3.2.3
SYSREF Request
8.3.4
Digital Delay
8.3.4.1
Fixed Digital Delay
8.3.4.1.1
Fixed Digital Delay Example
8.3.4.2
Dynamic Digital Delay
8.3.4.3
Single and Multiple Dynamic Digital Delay Example
8.3.5
SYSREF to Device Clock Alignment
8.3.6
Input Clock Switching
8.3.6.1
Input Clock Switching - Manual Mode
8.3.6.2
Input Clock Switching - Pin Select Mode
8.3.6.3
Input Clock Switching - Automatic Mode
8.3.7
Digital Lock Detect
8.3.7.1
Calculating Digital Lock Detect Frequency Accuracy
8.3.8
Holdover
8.3.8.1
Enable Holdover
8.3.8.1.1
Fixed (Manual) CPout1 Holdover Mode
8.3.8.1.2
Tracked CPout1 Holdover Mode
8.3.8.2
During Holdover
8.3.8.3
Exiting Holdover
8.3.8.4
Holdover Frequency Accuracy and DAC Performance
8.3.9
PLL2 Loop Filter
8.4
Device Functional Modes
8.4.1
DUAL PLL
8.4.1.1
Dual Loop
8.4.1.2
Dual Loop With Cascaded 0-Delay
8.4.1.3
Dual Loop With Nested 0-Delay
8.4.2
Single PLL
8.4.2.1
PLL2 Single Loop
8.4.2.2
PLL2 With External VCO
8.4.3
Distribution Mode
8.5
Programming
8.5.1
Recommended Programming Sequence
8.6
Register Maps
8.6.1
Register Map for Device Programming
8.6.2
Device Register Descriptions
8.6.2.1
System Functions
8.6.2.1.1
RESET, SPI_3WIRE_DIS
8.6.2.1.2
POWERDOWN
8.6.2.1.3
ID_DEVICE_TYPE
8.6.2.1.4
ID_PROD
8.6.2.1.5
ID_MASKREV
8.6.2.1.6
ID_VNDR
8.6.2.2
(0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
8.6.2.2.1
DCLKX_Y_DIV
8.6.2.2.2
DCLKX_Y_DDLY
8.6.2.2.3
CLKoutX_Y_PD, CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKX_Y_DDLY_PD, DCLKX_Y_DDLY[9:8], DCLKX_Y_DIV[9:8]
8.6.2.2.4
CLKoutX_SRC_MUX, CLKoutX_Y_PD, DCLKX_Y_BYP, DCLKX_Y_DCC, DCLKX_Y_POL, DCLKX_Y_HS
8.6.2.2.5
CLKoutY_SRC_MUX, SCLKX_Y_PD, SCLKX_Y_DIS_MODE, SCLKX_Y_POL, SCLKX_Y_HS
8.6.2.2.6
SCLKX_Y_ADLY_EN, SCLKX_Y_ADLY
8.6.2.2.7
SCLKX_Y_DDLY
8.6.2.2.8
CLKoutY_FMT, CLKoutX_FMT
8.6.2.3
SYSREF, SYNC, and Device Config
8.6.2.3.1
VCO_MUX, OSCout_MUX, OSCout_FMT
8.6.2.3.2
SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX
8.6.2.3.3
SYSREF_DIV
8.6.2.3.4
SYSREF_DDLY
8.6.2.3.5
SYSREF_PULSE_CNT
8.6.2.3.6
PLL2_RCLK_MUX, PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN
8.6.2.3.7
PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
8.6.2.3.8
DDLYdSYSREF_EN, DDLYdX_EN
8.6.2.3.9
DDLYd_STEP_CNT
8.6.2.3.10
SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
8.6.2.3.11
SYNC_DISSYSREF, SYNC_DISX
8.6.2.3.12
PLL1R_SYNC_EN, PLL1R_SYNC_SRC, PLL2R_SYNC_EN
8.6.2.4
(0x146 - 0x149) CLKin Control
8.6.2.4.1
CLKin_SEL_PIN_EN, CLKin_SEL_PIN_POL, CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
8.6.2.4.2
CLKin_SEL_AUTO_REVERT_EN, CLKin_SEL_AUTO_EN, CLKin_SEL_MANUAL, CLKin1_DEMUX, CLKin0_DEMUX
8.6.2.4.3
CLKin_SEL0_MUX, CLKin_SEL0_TYPE
8.6.2.4.4
SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
8.6.2.5
RESET_MUX, RESET_TYPE
8.6.2.6
(0x14B - 0x152) Holdover
8.6.2.6.1
LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
8.6.2.6.2
MAN_DAC
8.6.2.6.3
DAC_TRIP_LOW
8.6.2.6.4
DAC_CLK_MULT, DAC_TRIP_HIGH
8.6.2.6.5
DAC_CLK_CNTR
8.6.2.6.6
CLKin_OVERRIDE, HOLDOVER_EXIT_MODE, HOLDOVER_PLL1_DET, LOS_EXTERNAL_INPUT, HOLDOVER_VTUNE_DET, CLKin_SWITCH_CP_TRI, HOLDOVER_EN
8.6.2.6.7
HOLDOVER_DLD_CNT
8.6.2.7
(0x153 - 0x15F) PLL1 Configuration
8.6.2.7.1
CLKin0_R
8.6.2.7.2
CLKin1_R
8.6.2.7.3
CLKin2_R
8.6.2.7.4
PLL1_N
8.6.2.7.5
PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
8.6.2.7.6
PLL1_DLD_CNT
8.6.2.7.7
HOLDOVER_EXIT_NADJ
8.6.2.7.8
PLL1_LD_MUX, PLL1_LD_TYPE
8.6.2.8
(0x160 - 0x16E) PLL2 Configuration
8.6.2.8.1
PLL2_R
8.6.2.8.2
PLL2_P, OSCin_FREQ, PLL2_REF_2X_EN
8.6.2.8.3
PLL2_N_CAL
8.6.2.8.4
PLL2_N
8.6.2.8.5
PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
8.6.2.8.6
PLL2_DLD_CNT
8.6.2.8.7
PLL2_LD_MUX, PLL2_LD_TYPE
8.6.2.9
(0x16F - 0x555) Misc Registers
8.6.2.9.1
PLL2_PRE_PD, PLL2_PD
8.6.2.9.2
PLL1R_RST
8.6.2.9.3
CLR_PLL1_LD_LOST, CLR_PLL2_LD_LOST
8.6.2.9.4
RB_PLL1_LD_LOST, RB_PLL1_LD, RB_PLL2_LD_LOST, RB_PLL2_LD
8.6.2.9.5
RB_DAC_VALUE (MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
8.6.2.9.6
RB_DAC_VALUE
8.6.2.9.7
RB_HOLDOVER
8.6.2.9.8
SPI_LOCK
9
Application and Implementation
9.1
Application Information
9.1.1
Digital Lock Detect Frequency Accuracy
9.1.1.1
Minimum Lock Time Calculation Example
9.1.2
Driving CLKin AND OSCin Inputs
9.1.2.1
Driving CLKin and OSCin PINS With a Differential Source
9.1.2.2
Driving CLKin Pins With a Single-Ended Source
9.1.3
OSCin Doubler for Best Phase Noise Performance
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Device Selection
9.2.2.1.1
Clock Architect
9.2.2.2
Device Configuration and Simulation
9.2.2.3
Device Programming
9.2.3
Application Curves
9.3
Do's and Don'ts
9.3.1
Pin Connection Recommendations
10
Power Supply Recommendations
10.1
Current Consumption
11
Layout
11.1
Layout Guidelines
11.1.1
Thermal Management
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
デバイス・サポート
12.1.1
開発サポート
12.1.1.1
Clock Architect
12.1.1.2
PLLatinum Sim
12.1.1.3
TICS Pro
12.2
コミュニティ・リソース
12.3
商標
12.4
静電気放電に関する注意事項
12.5
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
NKD|64
MPQS032B
サーマルパッド・メカニカル・データ
NKD|64
QFND765
発注情報
jajsfi6c_oa
7.1
Charge Pump Current Specification Definitions
I1 = Charge Pump Sink Current at V
CPout
= V
CC
- ΔV
I2 = Charge Pump Sink Current at V
CPout
= V
CC
/2
I3 = Charge Pump Sink Current at V
CPout
= ΔV
I4 = Charge Pump Source Current at V
CPout
= V
CC
- ΔV
I5 = Charge Pump Source Current at V
CPout
= V
CC
/2
I6 = Charge Pump Source Current at V
CPout
= ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.