JAJSFI6C Februray 2017 – May 2018 LMK04832
PRODUCTION DATA.
The device clock dividers support a dynamic digital delay feature which allows the clock to be delayed by one full device clock cycle. With a single programming, an adjustment of up to 255 one cycle delays may occur. When making a multi-step adjustment, the adjustments are periodically applied to reduce impact to the clock.
Dynamic phase adjustments of half a clock distribution cycle are possible by half step.
The SYSREF digital delay value is reused for dynamic digital delay. To achieve a one cycle delay program the SYSREF digital delay value to one greater than half the SYSREF divide value.